diff mbox series

[1/1] RISC-V: correct enum sbi_ext_rfence_fid

Message ID 20210306054801.18263-1-xypron.glpk@gmx.de (mailing list archive)
State New, archived
Headers show
Series [1/1] RISC-V: correct enum sbi_ext_rfence_fid | expand

Commit Message

Heinrich Schuchardt March 6, 2021, 5:48 a.m. UTC 
The constants in enum sbi_ext_rfence_fid should match the SBI
specification. See
https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc#78-function-listing

| Function Name               | FID | EID
| sbi_remote_fence_i          |   0 | 0x52464E43
| sbi_remote_sfence_vma       |   1 | 0x52464E43
| sbi_remote_sfence_vma_asid  |   2 | 0x52464E43
| sbi_remote_hfence_gvma_vmid |   3 | 0x52464E43
| sbi_remote_hfence_gvma      |   4 | 0x52464E43
| sbi_remote_hfence_vvma_asid |   5 | 0x52464E43
| sbi_remote_hfence_vvma      |   6 | 0x52464E43

Fixes: ecbacc2a3efd ("RISC-V: Add SBI v0.2 extension definitions")
Reported-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
 arch/riscv/include/asm/sbi.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

--
2.30.1

Comments

Anup Patel March 6, 2021, 12:12 p.m. UTC | #1 
On Sat, Mar 6, 2021 at 11:19 AM Heinrich Schuchardt <xypron.glpk@gmx.de> wrote:
>
> The constants in enum sbi_ext_rfence_fid should match the SBI
> specification. See
> https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc#78-function-listing
>
> | Function Name               | FID | EID
> | sbi_remote_fence_i          |   0 | 0x52464E43
> | sbi_remote_sfence_vma       |   1 | 0x52464E43
> | sbi_remote_sfence_vma_asid  |   2 | 0x52464E43
> | sbi_remote_hfence_gvma_vmid |   3 | 0x52464E43
> | sbi_remote_hfence_gvma      |   4 | 0x52464E43
> | sbi_remote_hfence_vvma_asid |   5 | 0x52464E43
> | sbi_remote_hfence_vvma      |   6 | 0x52464E43
>
> Fixes: ecbacc2a3efd ("RISC-V: Add SBI v0.2 extension definitions")
> Reported-by: Sean Anderson <seanga2@gmail.com>
> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>

Good catch.

I guess we never saw any issues because these calls are only used by
KVM RISC-V which is not merged yet. Further for KVM RISC-V, the HFENCE
instruction is emulated as flush everything on FPGA, QEMU, and Spike so
we did not notice any issue with KVM RISC-V too.

Looks good to me.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup

> ---
>  arch/riscv/include/asm/sbi.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 99895d9c3bdd..d7027411dde8 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -51,10 +51,10 @@ enum sbi_ext_rfence_fid {
>         SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
>         SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
>         SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
> -       SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
>         SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
> -       SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
> +       SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
>         SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
> +       SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
>  };
>
>  enum sbi_ext_hsm_fid {
> --
> 2.30.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Atish Patra March 8, 2021, 7:49 a.m. UTC | #2 
On Sat, Mar 6, 2021 at 4:12 AM Anup Patel <anup@brainfault.org> wrote:
>
> On Sat, Mar 6, 2021 at 11:19 AM Heinrich Schuchardt <xypron.glpk@gmx.de> wrote:
> >
> > The constants in enum sbi_ext_rfence_fid should match the SBI
> > specification. See
> > https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc#78-function-listing
> >
> > | Function Name               | FID | EID
> > | sbi_remote_fence_i          |   0 | 0x52464E43
> > | sbi_remote_sfence_vma       |   1 | 0x52464E43
> > | sbi_remote_sfence_vma_asid  |   2 | 0x52464E43
> > | sbi_remote_hfence_gvma_vmid |   3 | 0x52464E43
> > | sbi_remote_hfence_gvma      |   4 | 0x52464E43
> > | sbi_remote_hfence_vvma_asid |   5 | 0x52464E43
> > | sbi_remote_hfence_vvma      |   6 | 0x52464E43
> >
> > Fixes: ecbacc2a3efd ("RISC-V: Add SBI v0.2 extension definitions")
> > Reported-by: Sean Anderson <seanga2@gmail.com>
> > Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
>
> Good catch.
>
> I guess we never saw any issues because these calls are only used by
> KVM RISC-V which is not merged yet. Further for KVM RISC-V, the HFENCE
> instruction is emulated as flush everything on FPGA, QEMU, and Spike so
> we did not notice any issue with KVM RISC-V too.
>

OpenSBI & Xvisor also define the same order as Linux kernel. The
existing order(in Linux kernel)
makes more sense w.r.to Lexicographic order as well.

Should we just fix the spec instead ?

> Looks good to me.
>
> Reviewed-by: Anup Patel <anup@brainfault.org>
>
> Regards,
> Anup
>
> > ---
> >  arch/riscv/include/asm/sbi.h | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> > index 99895d9c3bdd..d7027411dde8 100644
> > --- a/arch/riscv/include/asm/sbi.h
> > +++ b/arch/riscv/include/asm/sbi.h
> > @@ -51,10 +51,10 @@ enum sbi_ext_rfence_fid {
> >         SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
> >         SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
> >         SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
> > -       SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
> >         SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
> > -       SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
> > +       SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
> >         SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
> > +       SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
> >  };
> >
> >  enum sbi_ext_hsm_fid {
> > --
> > 2.30.1
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Atish Patra March 8, 2021, 8:03 a.m. UTC | #3 
On Sun, Mar 7, 2021 at 11:49 PM Atish Patra <atishp@atishpatra.org> wrote:
>
> On Sat, Mar 6, 2021 at 4:12 AM Anup Patel <anup@brainfault.org> wrote:
> >
> > On Sat, Mar 6, 2021 at 11:19 AM Heinrich Schuchardt <xypron.glpk@gmx.de> wrote:
> > >
> > > The constants in enum sbi_ext_rfence_fid should match the SBI
> > > specification. See
> > > https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc#78-function-listing
> > >
> > > | Function Name               | FID | EID
> > > | sbi_remote_fence_i          |   0 | 0x52464E43
> > > | sbi_remote_sfence_vma       |   1 | 0x52464E43
> > > | sbi_remote_sfence_vma_asid  |   2 | 0x52464E43
> > > | sbi_remote_hfence_gvma_vmid |   3 | 0x52464E43
> > > | sbi_remote_hfence_gvma      |   4 | 0x52464E43
> > > | sbi_remote_hfence_vvma_asid |   5 | 0x52464E43
> > > | sbi_remote_hfence_vvma      |   6 | 0x52464E43
> > >
> > > Fixes: ecbacc2a3efd ("RISC-V: Add SBI v0.2 extension definitions")
> > > Reported-by: Sean Anderson <seanga2@gmail.com>
> > > Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
> >
> > Good catch.
> >
> > I guess we never saw any issues because these calls are only used by
> > KVM RISC-V which is not merged yet. Further for KVM RISC-V, the HFENCE
> > instruction is emulated as flush everything on FPGA, QEMU, and Spike so
> > we did not notice any issue with KVM RISC-V too.
> >
>
> OpenSBI & Xvisor also define the same order as Linux kernel. The
> existing order(in Linux kernel)
> makes more sense w.r.to Lexicographic order as well.
>
> Should we just fix the spec instead ?
>

We do need to notify RustSBI & Diosix authors about this change in
case we decide to do so.
However, RustSBI added rfence support a few weeks back only [1]. I
could not find any rfence reference in Diosix.
Thus, the impact should be very minimal if the spec is fixed.

[1] https://github.com/luojia65/rustsbi/commit/6e06b4e8e96e05b69157dd5477d433cc932c8a64
> > Looks good to me.
> >
> > Reviewed-by: Anup Patel <anup@brainfault.org>
> >
> > Regards,
> > Anup
> >
> > > ---
> > >  arch/riscv/include/asm/sbi.h | 4 ++--
> > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> > > index 99895d9c3bdd..d7027411dde8 100644
> > > --- a/arch/riscv/include/asm/sbi.h
> > > +++ b/arch/riscv/include/asm/sbi.h
> > > @@ -51,10 +51,10 @@ enum sbi_ext_rfence_fid {
> > >         SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
> > >         SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
> > >         SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
> > > -       SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
> > >         SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
> > > -       SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
> > > +       SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
> > >         SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
> > > +       SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
> > >  };
> > >
> > >  enum sbi_ext_hsm_fid {
> > > --
> > > 2.30.1
> > >
> > >
> > > _______________________________________________
> > > linux-riscv mailing list
> > > linux-riscv@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-riscv
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
>
>
>
> --
> Regards,
> Atish
Anup Patel March 8, 2021, 10:55 a.m. UTC | #4 
On Mon, Mar 8, 2021 at 1:19 PM Atish Patra <atishp@atishpatra.org> wrote:
>
> On Sat, Mar 6, 2021 at 4:12 AM Anup Patel <anup@brainfault.org> wrote:
> >
> > On Sat, Mar 6, 2021 at 11:19 AM Heinrich Schuchardt <xypron.glpk@gmx.de> wrote:
> > >
> > > The constants in enum sbi_ext_rfence_fid should match the SBI
> > > specification. See
> > > https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc#78-function-listing
> > >
> > > | Function Name               | FID | EID
> > > | sbi_remote_fence_i          |   0 | 0x52464E43
> > > | sbi_remote_sfence_vma       |   1 | 0x52464E43
> > > | sbi_remote_sfence_vma_asid  |   2 | 0x52464E43
> > > | sbi_remote_hfence_gvma_vmid |   3 | 0x52464E43
> > > | sbi_remote_hfence_gvma      |   4 | 0x52464E43
> > > | sbi_remote_hfence_vvma_asid |   5 | 0x52464E43
> > > | sbi_remote_hfence_vvma      |   6 | 0x52464E43
> > >
> > > Fixes: ecbacc2a3efd ("RISC-V: Add SBI v0.2 extension definitions")
> > > Reported-by: Sean Anderson <seanga2@gmail.com>
> > > Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
> >
> > Good catch.
> >
> > I guess we never saw any issues because these calls are only used by
> > KVM RISC-V which is not merged yet. Further for KVM RISC-V, the HFENCE
> > instruction is emulated as flush everything on FPGA, QEMU, and Spike so
> > we did not notice any issue with KVM RISC-V too.
> >
>
> OpenSBI & Xvisor also define the same order as Linux kernel. The
> existing order(in Linux kernel)
> makes more sense w.r.to Lexicographic order as well.
>
> Should we just fix the spec instead ?

I would not recommend that because RFENCE is part of the released SBI v0.2 spec.

We have to be more careful in software to follow the spec correctly.

Regards,
Anup

>
> > Looks good to me.
> >
> > Reviewed-by: Anup Patel <anup@brainfault.org>
> >
> > Regards,
> > Anup
> >
> > > ---
> > >  arch/riscv/include/asm/sbi.h | 4 ++--
> > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> > > index 99895d9c3bdd..d7027411dde8 100644
> > > --- a/arch/riscv/include/asm/sbi.h
> > > +++ b/arch/riscv/include/asm/sbi.h
> > > @@ -51,10 +51,10 @@ enum sbi_ext_rfence_fid {
> > >         SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
> > >         SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
> > >         SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
> > > -       SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
> > >         SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
> > > -       SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
> > > +       SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
> > >         SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
> > > +       SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
> > >  };
> > >
> > >  enum sbi_ext_hsm_fid {
> > > --
> > > 2.30.1
> > >
> > >
> > > _______________________________________________
> > > linux-riscv mailing list
> > > linux-riscv@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-riscv
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
>
>
>
> --
> Regards,
> Atish
Heinrich Schuchardt March 9, 2021, 11:33 a.m. UTC | #5 
On 08.03.21 11:55, Anup Patel wrote:
> On Mon, Mar 8, 2021 at 1:19 PM Atish Patra <atishp@atishpatra.org> wrote:
>>
>> On Sat, Mar 6, 2021 at 4:12 AM Anup Patel <anup@brainfault.org> wrote:
>>>
>>> On Sat, Mar 6, 2021 at 11:19 AM Heinrich Schuchardt <xypron.glpk@gmx.de> wrote:
>>>>
>>>> The constants in enum sbi_ext_rfence_fid should match the SBI
>>>> specification. See
>>>> https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc#78-function-listing
>>>>
>>>> | Function Name               | FID | EID
>>>> | sbi_remote_fence_i          |   0 | 0x52464E43
>>>> | sbi_remote_sfence_vma       |   1 | 0x52464E43
>>>> | sbi_remote_sfence_vma_asid  |   2 | 0x52464E43
>>>> | sbi_remote_hfence_gvma_vmid |   3 | 0x52464E43
>>>> | sbi_remote_hfence_gvma      |   4 | 0x52464E43
>>>> | sbi_remote_hfence_vvma_asid |   5 | 0x52464E43
>>>> | sbi_remote_hfence_vvma      |   6 | 0x52464E43
>>>>
>>>> Fixes: ecbacc2a3efd ("RISC-V: Add SBI v0.2 extension definitions")
>>>> Reported-by: Sean Anderson <seanga2@gmail.com>
>>>> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
>>>
>>> Good catch.
>>>
>>> I guess we never saw any issues because these calls are only used by
>>> KVM RISC-V which is not merged yet. Further for KVM RISC-V, the HFENCE
>>> instruction is emulated as flush everything on FPGA, QEMU, and Spike so
>>> we did not notice any issue with KVM RISC-V too.
>>>
>>
>> OpenSBI & Xvisor also define the same order as Linux kernel. The
>> existing order(in Linux kernel)
>> makes more sense w.r.to Lexicographic order as well.

Here is the OpenSBI correction:

[PATCH 1/1] include: sbi: SBI function IDs for RFENCE extension
http://lists.infradead.org/pipermail/opensbi/2021-March/000703.html

Best regards

Heinrich

>>
>> Should we just fix the spec instead ?
>
> I would not recommend that because RFENCE is part of the released SBI v0.2 spec.
>
> We have to be more careful in software to follow the spec correctly.
>
> Regards,
> Anup
>
>>
>>> Looks good to me.
>>>
>>> Reviewed-by: Anup Patel <anup@brainfault.org>
>>>
>>> Regards,
>>> Anup
>>>
>>>> ---
>>>>  arch/riscv/include/asm/sbi.h | 4 ++--
>>>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
>>>> index 99895d9c3bdd..d7027411dde8 100644
>>>> --- a/arch/riscv/include/asm/sbi.h
>>>> +++ b/arch/riscv/include/asm/sbi.h
>>>> @@ -51,10 +51,10 @@ enum sbi_ext_rfence_fid {
>>>>         SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
>>>>         SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
>>>>         SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
>>>> -       SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
>>>>         SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
>>>> -       SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
>>>> +       SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
>>>>         SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
>>>> +       SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
>>>>  };
>>>>
>>>>  enum sbi_ext_hsm_fid {
>>>> --
>>>> 2.30.1
>>>>
>>>>
>>>> _______________________________________________
>>>> linux-riscv mailing list
>>>> linux-riscv@lists.infradead.org
>>>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>>>
>>> _______________________________________________
>>> linux-riscv mailing list
>>> linux-riscv@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>>
>>
>>
>> --
>> Regards,
>> Atish
Atish Patra March 9, 2021, 7:28 p.m. UTC | #6 
On Mon, Mar 8, 2021 at 2:55 AM Anup Patel <anup@brainfault.org> wrote:
>
> On Mon, Mar 8, 2021 at 1:19 PM Atish Patra <atishp@atishpatra.org> wrote:
> >
> > On Sat, Mar 6, 2021 at 4:12 AM Anup Patel <anup@brainfault.org> wrote:
> > >
> > > On Sat, Mar 6, 2021 at 11:19 AM Heinrich Schuchardt <xypron.glpk@gmx.de> wrote:
> > > >
> > > > The constants in enum sbi_ext_rfence_fid should match the SBI
> > > > specification. See
> > > > https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc#78-function-listing
> > > >
> > > > | Function Name               | FID | EID
> > > > | sbi_remote_fence_i          |   0 | 0x52464E43
> > > > | sbi_remote_sfence_vma       |   1 | 0x52464E43
> > > > | sbi_remote_sfence_vma_asid  |   2 | 0x52464E43
> > > > | sbi_remote_hfence_gvma_vmid |   3 | 0x52464E43
> > > > | sbi_remote_hfence_gvma      |   4 | 0x52464E43
> > > > | sbi_remote_hfence_vvma_asid |   5 | 0x52464E43
> > > > | sbi_remote_hfence_vvma      |   6 | 0x52464E43
> > > >
> > > > Fixes: ecbacc2a3efd ("RISC-V: Add SBI v0.2 extension definitions")
> > > > Reported-by: Sean Anderson <seanga2@gmail.com>
> > > > Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
> > >

Reviewed-by: Atish Patra <atish.patra@wdc.com>

> > > Good catch.
> > >
> > > I guess we never saw any issues because these calls are only used by
> > > KVM RISC-V which is not merged yet. Further for KVM RISC-V, the HFENCE
> > > instruction is emulated as flush everything on FPGA, QEMU, and Spike so
> > > we did not notice any issue with KVM RISC-V too.
> > >
> >
> > OpenSBI & Xvisor also define the same order as Linux kernel. The
> > existing order(in Linux kernel)
> > makes more sense w.r.to Lexicographic order as well.
> >
> > Should we just fix the spec instead ?
>
> I would not recommend that because RFENCE is part of the released SBI v0.2 spec.
>

Fair enough.

> We have to be more careful in software to follow the spec correctly.
>

Agreed. Apologies for the slip up.

> Regards,
> Anup
>
> >
> > > Looks good to me.
> > >
> > > Reviewed-by: Anup Patel <anup@brainfault.org>
> > >
> > > Regards,
> > > Anup
> > >
> > > > ---
> > > >  arch/riscv/include/asm/sbi.h | 4 ++--
> > > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> > > > index 99895d9c3bdd..d7027411dde8 100644
> > > > --- a/arch/riscv/include/asm/sbi.h
> > > > +++ b/arch/riscv/include/asm/sbi.h
> > > > @@ -51,10 +51,10 @@ enum sbi_ext_rfence_fid {
> > > >         SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
> > > >         SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
> > > >         SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
> > > > -       SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
> > > >         SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
> > > > -       SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
> > > > +       SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
> > > >         SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
> > > > +       SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
> > > >  };
> > > >
> > > >  enum sbi_ext_hsm_fid {
> > > > --
> > > > 2.30.1
> > > >
> > > >
> > > > _______________________________________________
> > > > linux-riscv mailing list
> > > > linux-riscv@lists.infradead.org
> > > > http://lists.infradead.org/mailman/listinfo/linux-riscv
> > >
> > > _______________________________________________
> > > linux-riscv mailing list
> > > linux-riscv@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-riscv
> >
> >
> >
> > --
> > Regards,
> > Atish
Palmer Dabbelt March 10, 2021, 3:23 a.m. UTC | #7 
On Tue, 09 Mar 2021 11:28:39 PST (-0800), atishp@atishpatra.org wrote:
> On Mon, Mar 8, 2021 at 2:55 AM Anup Patel <anup@brainfault.org> wrote:
>>
>> On Mon, Mar 8, 2021 at 1:19 PM Atish Patra <atishp@atishpatra.org> wrote:
>> >
>> > On Sat, Mar 6, 2021 at 4:12 AM Anup Patel <anup@brainfault.org> wrote:
>> > >
>> > > On Sat, Mar 6, 2021 at 11:19 AM Heinrich Schuchardt <xypron.glpk@gmx.de> wrote:
>> > > >
>> > > > The constants in enum sbi_ext_rfence_fid should match the SBI
>> > > > specification. See
>> > > > https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc#78-function-listing
>> > > >
>> > > > | Function Name               | FID | EID
>> > > > | sbi_remote_fence_i          |   0 | 0x52464E43
>> > > > | sbi_remote_sfence_vma       |   1 | 0x52464E43
>> > > > | sbi_remote_sfence_vma_asid  |   2 | 0x52464E43
>> > > > | sbi_remote_hfence_gvma_vmid |   3 | 0x52464E43
>> > > > | sbi_remote_hfence_gvma      |   4 | 0x52464E43
>> > > > | sbi_remote_hfence_vvma_asid |   5 | 0x52464E43
>> > > > | sbi_remote_hfence_vvma      |   6 | 0x52464E43
>> > > >
>> > > > Fixes: ecbacc2a3efd ("RISC-V: Add SBI v0.2 extension definitions")
>> > > > Reported-by: Sean Anderson <seanga2@gmail.com>
>> > > > Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
>> > >
>
> Reviewed-by: Atish Patra <atish.patra@wdc.com>
>
>> > > Good catch.
>> > >
>> > > I guess we never saw any issues because these calls are only used by
>> > > KVM RISC-V which is not merged yet. Further for KVM RISC-V, the HFENCE
>> > > instruction is emulated as flush everything on FPGA, QEMU, and Spike so
>> > > we did not notice any issue with KVM RISC-V too.
>> > >
>> >
>> > OpenSBI & Xvisor also define the same order as Linux kernel. The
>> > existing order(in Linux kernel)
>> > makes more sense w.r.to Lexicographic order as well.
>> >
>> > Should we just fix the spec instead ?
>>
>> I would not recommend that because RFENCE is part of the released SBI v0.2 spec.
>>
>
> Fair enough.

Yes, agreed.  It's very important that we don't change the specs we said are 
frozen, that would be a huge mess.

This is on fixes.

Thanks!

>
>> We have to be more careful in software to follow the spec correctly.
>>
>
> Agreed. Apologies for the slip up.
>
>> Regards,
>> Anup
>>
>> >
>> > > Looks good to me.
>> > >
>> > > Reviewed-by: Anup Patel <anup@brainfault.org>
>> > >
>> > > Regards,
>> > > Anup
>> > >
>> > > > ---
>> > > >  arch/riscv/include/asm/sbi.h | 4 ++--
>> > > >  1 file changed, 2 insertions(+), 2 deletions(-)
>> > > >
>> > > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
>> > > > index 99895d9c3bdd..d7027411dde8 100644
>> > > > --- a/arch/riscv/include/asm/sbi.h
>> > > > +++ b/arch/riscv/include/asm/sbi.h
>> > > > @@ -51,10 +51,10 @@ enum sbi_ext_rfence_fid {
>> > > >         SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
>> > > >         SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
>> > > >         SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
>> > > > -       SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
>> > > >         SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
>> > > > -       SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
>> > > > +       SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
>> > > >         SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
>> > > > +       SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
>> > > >  };
>> > > >
>> > > >  enum sbi_ext_hsm_fid {
>> > > > --
>> > > > 2.30.1
>> > > >
>> > > >
>> > > > _______________________________________________
>> > > > linux-riscv mailing list
>> > > > linux-riscv@lists.infradead.org
>> > > > http://lists.infradead.org/mailman/listinfo/linux-riscv
>> > >
>> > > _______________________________________________
>> > > linux-riscv mailing list
>> > > linux-riscv@lists.infradead.org
>> > > http://lists.infradead.org/mailman/listinfo/linux-riscv
>> >
>> >
>> >
>> > --
>> > Regards,
>> > Atish
diff mbox series

Patch

diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 99895d9c3bdd..d7027411dde8 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -51,10 +51,10 @@  enum sbi_ext_rfence_fid {
 	SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
 	SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
 	SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
-	SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
 	SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
-	SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
+	SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
 	SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
+	SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
 };

 enum sbi_ext_hsm_fid {