[v2,0/2] tests/acceptance: Test Aspeed ARM machines

Message

Joel Stanley March 4, 2021, 12:39 p.m. UTC

v2: Fix ast2600 test, thanks Cédric for the review.

This adds tests for the Aspeed ARM SoCs. The AST2400 and AST2500 tests
use OpenBMC images from that project, fetched from github releases. The
AST2600 test uses a Debian arm32 kernel.

Note that the ast2600 test will fail if [1] is not applied. I have
tested locally and all seems good.

I note that checkpatch warns about a couple of lines over 80 columns in
this file.  Can we agree to relax this restriction for this file, as it
helps the readability of the constants such as sha hashes and URLs?

[1] https://lore.kernel.org/qemu-devel/[e-mail]/T/#u

Joel Stanley (2):
  tests/acceptance: Test ast2400 and ast2500 machines
  tests/acceptance: Test ast2600 machine

 tests/acceptance/boot_linux_console.py | 72 ++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

Comments

Peter Maydell March 5, 2021, 3:12 p.m. UTC | #1

On Thu, 4 Mar 2021 at 12:40, Joel Stanley <[e-mail]> wrote:
>
> v2: Fix ast2600 test, thanks Cédric for the review.
>
> This adds tests for the Aspeed ARM SoCs. The AST2400 and AST2500 tests
> use OpenBMC images from that project, fetched from github releases. The
> AST2600 test uses a Debian arm32 kernel.

Just a note that I'm assuming that Cédric will gather up the
various aspeed related patches that have been on the list recently
and send a pullreq for them. (Having been on holiday my to-review
queue is pretty full so I've just ignored anything aspeed-related;
let me know if there is anything you specifically want me to look
at, queue, whatever.)

PS: softfreeze is 16 March so a pullreq on list sometime next week
would probably be the ideal.

thanks
-- PMM

Cédric Le Goater March 5, 2021, 3:38 p.m. UTC | #2

On 3/5/21 4:12 PM, Peter Maydell wrote:
> On Thu, 4 Mar 2021 at 12:40, Joel Stanley <[e-mail]> wrote:
>>
>> v2: Fix ast2600 test, thanks Cédric for the review.
>>
>> This adds tests for the Aspeed ARM SoCs. The AST2400 and AST2500 tests
>> use OpenBMC images from that project, fetched from github releases. The
>> AST2600 test uses a Debian arm32 kernel.
> 
> Just a note that I'm assuming that Cédric will gather up the
> various aspeed related patches that have been on the list recently
> and send a pullreq for them. (Having been on holiday my to-review
> queue is pretty full so I've just ignored anything aspeed-related;
> let me know if there is anything you specifically want me to look
> at, queue, whatever.)
>
> PS: softfreeze is 16 March so a pullreq on list sometime next week
> would probably be the ideal.

Yes. I am preparing the PR. 

  aspeed: Integrate HACE
  hw: Model ASPEED's Hash and Crypto Engine
  hw/misc: Model KCS devices in the Aspeed LPC controller
  hw/misc: Add a basic Aspeed LPC controller model
  hw/arm: ast2600: Correct the iBT interrupt ID
  hw/arm: ast2600: Set AST2600_MAX_IRQ to value from datasheet
  hw/arm: ast2600: Force a multiple of 32 of IRQs for the GIC
  hw/arm/aspeed: Fix location of firmware images in documentation
  aspeed: Emulate the AST2600A3
  tests/acceptance: Test ast2600 machine
  tests/acceptance: Test ast2400 and ast2500 machines
  arm/ast2600: Fix SMP booting with -kernel

The HACE patchset needs a second look from an Aspeed-aware person and 
I have some questions on AST2600A3.

Merging these acceptance tests would be really nice. Have we addressed
all you concerns Philippe regarding the image downloads ?

Thanks,

C.

Philippe Mathieu-Daudé March 9, 2021, 9:43 a.m. UTC | #3

+Alex

On 3/5/21 4:38 PM, Cédric Le Goater wrote:
> On 3/5/21 4:12 PM, Peter Maydell wrote:
>> On Thu, 4 Mar 2021 at 12:40, Joel Stanley <[e-mail]> wrote:
>>>
>>> v2: Fix ast2600 test, thanks Cédric for the review.
>>>
>>> This adds tests for the Aspeed ARM SoCs. The AST2400 and AST2500 tests
>>> use OpenBMC images from that project, fetched from github releases. The
>>> AST2600 test uses a Debian arm32 kernel.
>>
>> Just a note that I'm assuming that Cédric will gather up the
>> various aspeed related patches that have been on the list recently
>> and send a pullreq for them. (Having been on holiday my to-review
>> queue is pretty full so I've just ignored anything aspeed-related;
>> let me know if there is anything you specifically want me to look
>> at, queue, whatever.)
>>
>> PS: softfreeze is 16 March so a pullreq on list sometime next week
>> would probably be the ideal.
> 
> Yes. I am preparing the PR. 
> 
>   aspeed: Integrate HACE
>   hw: Model ASPEED's Hash and Crypto Engine
>   hw/misc: Model KCS devices in the Aspeed LPC controller
>   hw/misc: Add a basic Aspeed LPC controller model
>   hw/arm: ast2600: Correct the iBT interrupt ID
>   hw/arm: ast2600: Set AST2600_MAX_IRQ to value from datasheet
>   hw/arm: ast2600: Force a multiple of 32 of IRQs for the GIC
>   hw/arm/aspeed: Fix location of firmware images in documentation
>   aspeed: Emulate the AST2600A3
>   tests/acceptance: Test ast2600 machine
>   tests/acceptance: Test ast2400 and ast2500 machines
>   arm/ast2600: Fix SMP booting with -kernel
> 
> The HACE patchset needs a second look from an Aspeed-aware person and 
> I have some questions on AST2600A3.
> 
> Merging these acceptance tests would be really nice. Have we addressed
> all you concerns Philippe regarding the image downloads ?

No, but I'll defer to Alex here:
https://www.mail-archive.com/[e-mail]/msg787742.html

> 
> Thanks,
> 
> C.
>