| Message ID | 20210301084257.945454-15-hch@lst.de (mailing list archive) |
|---|---|
| State | Not Applicable |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | [01/17] iommu: remove the unused domain_window_disable method | expand |
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Not a local patch |
On 2021-03-01 08:42, Christoph Hellwig wrote: > Use explicit methods for setting and querying the information instead. Now that everyone's using iommu-dma, is there any point in bouncing this through the drivers at all? Seems like it would make more sense for the x86 drivers to reflect their private options back to iommu_dma_strict (and allow Intel's caching mode to override it as well), then have iommu_dma_init_domain just test !iommu_dma_strict && domain->ops->flush_iotlb_all. Robin. > Also remove the now unused iommu_domain_get_attr functionality. > > Signed-off-by: Christoph Hellwig <hch@lst.de> > --- > drivers/iommu/amd/iommu.c | 23 ++------- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 47 ++++++----------- > drivers/iommu/arm/arm-smmu/arm-smmu.c | 56 +++++---------------- > drivers/iommu/dma-iommu.c | 8 ++- > drivers/iommu/intel/iommu.c | 27 ++-------- > drivers/iommu/iommu.c | 19 +++---- > include/linux/iommu.h | 17 ++----- > 7 files changed, 51 insertions(+), 146 deletions(-) > > diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c > index a69a8b573e40d0..37a8e51db17656 100644 > --- a/drivers/iommu/amd/iommu.c > +++ b/drivers/iommu/amd/iommu.c > @@ -1771,24 +1771,11 @@ static struct iommu_group *amd_iommu_device_group(struct device *dev) > return acpihid_device_group(dev); > } > > -static int amd_iommu_domain_get_attr(struct iommu_domain *domain, > - enum iommu_attr attr, void *data) > +static bool amd_iommu_dma_use_flush_queue(struct iommu_domain *domain) > { > - switch (domain->type) { > - case IOMMU_DOMAIN_UNMANAGED: > - return -ENODEV; > - case IOMMU_DOMAIN_DMA: > - switch (attr) { > - case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE: > - *(int *)data = !amd_iommu_unmap_flush; > - return 0; > - default: > - return -ENODEV; > - } > - break; > - default: > - return -EINVAL; > - } > + if (domain->type != IOMMU_DOMAIN_DMA) > + return false; > + return !amd_iommu_unmap_flush; > } > > /***************************************************************************** > @@ -2257,7 +2244,7 @@ const struct iommu_ops amd_iommu_ops = { > .release_device = amd_iommu_release_device, > .probe_finalize = amd_iommu_probe_finalize, > .device_group = amd_iommu_device_group, > - .domain_get_attr = amd_iommu_domain_get_attr, > + .dma_use_flush_queue = amd_iommu_dma_use_flush_queue, > .get_resv_regions = amd_iommu_get_resv_regions, > .put_resv_regions = generic_iommu_put_resv_regions, > .is_attach_deferred = amd_iommu_is_attach_deferred, > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 8594b4a8304375..bf96172e8c1f71 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -2449,33 +2449,21 @@ static struct iommu_group *arm_smmu_device_group(struct device *dev) > return group; > } > > -static int arm_smmu_domain_get_attr(struct iommu_domain *domain, > - enum iommu_attr attr, void *data) > +static bool arm_smmu_dma_use_flush_queue(struct iommu_domain *domain) > { > struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); > > - switch (domain->type) { > - case IOMMU_DOMAIN_UNMANAGED: > - switch (attr) { > - case DOMAIN_ATTR_NESTING: > - *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED); > - return 0; > - default: > - return -ENODEV; > - } > - break; > - case IOMMU_DOMAIN_DMA: > - switch (attr) { > - case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE: > - *(int *)data = smmu_domain->non_strict; > - return 0; > - default: > - return -ENODEV; > - } > - break; > - default: > - return -EINVAL; > - } > + if (domain->type != IOMMU_DOMAIN_DMA) > + return false; > + return smmu_domain->non_strict; > +} > + > + > +static void arm_smmu_dma_enable_flush_queue(struct iommu_domain *domain) > +{ > + if (domain->type != IOMMU_DOMAIN_DMA) > + return; > + to_smmu_domain(domain)->non_strict = true; > } > > static int arm_smmu_domain_set_attr(struct iommu_domain *domain, > @@ -2505,13 +2493,7 @@ static int arm_smmu_domain_set_attr(struct iommu_domain *domain, > } > break; > case IOMMU_DOMAIN_DMA: > - switch(attr) { > - case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE: > - smmu_domain->non_strict = *(int *)data; > - break; > - default: > - ret = -ENODEV; > - } > + ret = -ENODEV; > break; > default: > ret = -EINVAL; > @@ -2619,7 +2601,8 @@ static struct iommu_ops arm_smmu_ops = { > .probe_device = arm_smmu_probe_device, > .release_device = arm_smmu_release_device, > .device_group = arm_smmu_device_group, > - .domain_get_attr = arm_smmu_domain_get_attr, > + .dma_use_flush_queue = arm_smmu_dma_use_flush_queue, > + .dma_enable_flush_queue = arm_smmu_dma_enable_flush_queue, > .domain_set_attr = arm_smmu_domain_set_attr, > .of_xlate = arm_smmu_of_xlate, > .get_resv_regions = arm_smmu_get_resv_regions, > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c > index d8c6bfde6a6158..e7893e96f5177a 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c > @@ -1481,42 +1481,20 @@ static struct iommu_group *arm_smmu_device_group(struct device *dev) > return group; > } > > -static int arm_smmu_domain_get_attr(struct iommu_domain *domain, > - enum iommu_attr attr, void *data) > +static bool arm_smmu_dma_use_flush_queue(struct iommu_domain *domain) > { > struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); > > - switch(domain->type) { > - case IOMMU_DOMAIN_UNMANAGED: > - switch (attr) { > - case DOMAIN_ATTR_NESTING: > - *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED); > - return 0; > - case DOMAIN_ATTR_IO_PGTABLE_CFG: { > - struct io_pgtable_domain_attr *pgtbl_cfg = data; > - *pgtbl_cfg = smmu_domain->pgtbl_cfg; > + if (domain->type != IOMMU_DOMAIN_DMA) > + return false; > + return smmu_domain->pgtbl_cfg.quirks & IO_PGTABLE_QUIRK_NON_STRICT; > +} > > - return 0; > - } > - default: > - return -ENODEV; > - } > - break; > - case IOMMU_DOMAIN_DMA: > - switch (attr) { > - case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE: { > - bool non_strict = smmu_domain->pgtbl_cfg.quirks & > - IO_PGTABLE_QUIRK_NON_STRICT; > - *(int *)data = non_strict; > - return 0; > - } > - default: > - return -ENODEV; > - } > - break; > - default: > - return -EINVAL; > - } > +static void arm_smmu_dma_enable_flush_queue(struct iommu_domain *domain) > +{ > + if (domain->type != IOMMU_DOMAIN_DMA) > + return; > + to_smmu_domain(domain)->pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT; > } > > static int arm_smmu_domain_set_attr(struct iommu_domain *domain, > @@ -1557,16 +1535,7 @@ static int arm_smmu_domain_set_attr(struct iommu_domain *domain, > } > break; > case IOMMU_DOMAIN_DMA: > - switch (attr) { > - case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE: > - if (*(int *)data) > - smmu_domain->pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT; > - else > - smmu_domain->pgtbl_cfg.quirks &= ~IO_PGTABLE_QUIRK_NON_STRICT; > - break; > - default: > - ret = -ENODEV; > - } > + ret = -ENODEV; > break; > default: > ret = -EINVAL; > @@ -1631,7 +1600,8 @@ static struct iommu_ops arm_smmu_ops = { > .probe_device = arm_smmu_probe_device, > .release_device = arm_smmu_release_device, > .device_group = arm_smmu_device_group, > - .domain_get_attr = arm_smmu_domain_get_attr, > + .dma_use_flush_queue = arm_smmu_dma_use_flush_queue, > + .dma_enable_flush_queue = arm_smmu_dma_enable_flush_queue, > .domain_set_attr = arm_smmu_domain_set_attr, > .of_xlate = arm_smmu_of_xlate, > .get_resv_regions = arm_smmu_get_resv_regions, > diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c > index 9ab6ee22c11088..d3fe5aad9d6ecf 100644 > --- a/drivers/iommu/dma-iommu.c > +++ b/drivers/iommu/dma-iommu.c > @@ -305,8 +305,8 @@ static void iommu_dma_flush_iotlb_all(struct iova_domain *iovad) > cookie = container_of(iovad, struct iommu_dma_cookie, iovad); > domain = cookie->fq_domain; > /* > - * The IOMMU driver supporting DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE > - * implies that ops->flush_iotlb_all must be non-NULL. > + * The IOMMU driver supporting a DMA flush queue implies that > + * ops->flush_iotlb_all must be non-NULL. > */ > domain->ops->flush_iotlb_all(domain); > } > @@ -329,7 +329,6 @@ static int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base, > struct iommu_dma_cookie *cookie = domain->iova_cookie; > unsigned long order, base_pfn; > struct iova_domain *iovad; > - int attr; > > if (!cookie || cookie->type != IOMMU_DMA_IOVA_COOKIE) > return -EINVAL; > @@ -365,8 +364,7 @@ static int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base, > > init_iova_domain(iovad, 1UL << order, base_pfn); > > - if (!cookie->fq_domain && !iommu_domain_get_attr(domain, > - DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, &attr) && attr) { > + if (!cookie->fq_domain && iommu_dma_use_flush_queue(domain)) { > if (init_iova_flush_queue(iovad, iommu_dma_flush_iotlb_all, > iommu_dma_entry_dtor)) > pr_warn("iova flush queue initialization failed\n"); > diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c > index ee0932307d646b..eaa80c33f4bc91 100644 > --- a/drivers/iommu/intel/iommu.c > +++ b/drivers/iommu/intel/iommu.c > @@ -5453,13 +5453,13 @@ intel_iommu_domain_set_attr(struct iommu_domain *domain, > return ret; > } > > -static bool domain_use_flush_queue(void) > +static bool intel_iommu_dma_use_flush_queue(struct iommu_domain *domain) > { > struct dmar_drhd_unit *drhd; > struct intel_iommu *iommu; > bool r = true; > > - if (intel_iommu_strict) > + if (domain->type != IOMMU_DOMAIN_DMA || intel_iommu_strict) > return false; > > /* > @@ -5483,27 +5483,6 @@ static bool domain_use_flush_queue(void) > return r; > } > > -static int > -intel_iommu_domain_get_attr(struct iommu_domain *domain, > - enum iommu_attr attr, void *data) > -{ > - switch (domain->type) { > - case IOMMU_DOMAIN_UNMANAGED: > - return -ENODEV; > - case IOMMU_DOMAIN_DMA: > - switch (attr) { > - case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE: > - *(int *)data = domain_use_flush_queue(); > - return 0; > - default: > - return -ENODEV; > - } > - break; > - default: > - return -EINVAL; > - } > -} > - > /* > * Check that the device does not live on an external facing PCI port that is > * marked as untrusted. Such devices should not be able to apply quirks and > @@ -5576,7 +5555,7 @@ const struct iommu_ops intel_iommu_ops = { > .capable = intel_iommu_capable, > .domain_alloc = intel_iommu_domain_alloc, > .domain_free = intel_iommu_domain_free, > - .domain_get_attr = intel_iommu_domain_get_attr, > + .dma_use_flush_queue = intel_iommu_dma_use_flush_queue, > .domain_set_attr = intel_iommu_domain_set_attr, > .attach_dev = intel_iommu_attach_device, > .detach_dev = intel_iommu_detach_device, > diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c > index 23daaea7883b75..0f12c4d58cdc42 100644 > --- a/drivers/iommu/iommu.c > +++ b/drivers/iommu/iommu.c > @@ -1512,12 +1512,8 @@ static int iommu_group_alloc_default_domain(struct bus_type *bus, > if (!group->domain) > group->domain = dom; > > - if (!iommu_dma_strict) { > - int attr = 1; > - iommu_domain_set_attr(dom, > - DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, > - &attr); > - } > + if (!iommu_dma_strict && dom->ops->dma_enable_flush_queue) > + dom->ops->dma_enable_flush_queue(dom); > > return 0; > } > @@ -2664,14 +2660,13 @@ static int __init iommu_init(void) > } > core_initcall(iommu_init); > > -int iommu_domain_get_attr(struct iommu_domain *domain, > - enum iommu_attr attr, void *data) > +bool iommu_dma_use_flush_queue(struct iommu_domain *domain) > { > - if (!domain->ops->domain_get_attr) > - return -EINVAL; > - return domain->ops->domain_get_attr(domain, attr, data); > + if (!domain->ops->dma_use_flush_queue) > + return false; > + return domain->ops->dma_use_flush_queue(domain); > } > -EXPORT_SYMBOL_GPL(iommu_domain_get_attr); > +EXPORT_SYMBOL_GPL(iommu_dma_use_flush_queue); > > int iommu_domain_set_attr(struct iommu_domain *domain, > enum iommu_attr attr, void *data) > diff --git a/include/linux/iommu.h b/include/linux/iommu.h > index c15a8658daad64..f30de33c6ff56e 100644 > --- a/include/linux/iommu.h > +++ b/include/linux/iommu.h > @@ -108,7 +108,6 @@ enum iommu_cap { > > enum iommu_attr { > DOMAIN_ATTR_NESTING, /* two stages of translation */ > - DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, > DOMAIN_ATTR_IO_PGTABLE_CFG, > DOMAIN_ATTR_MAX, > }; > @@ -194,7 +193,8 @@ struct iommu_iotlb_gather { > * @probe_finalize: Do final setup work after the device is added to an IOMMU > * group and attached to the groups domain > * @device_group: find iommu group for a particular device > - * @domain_get_attr: Query domain attributes > + * @dma_use_flush_queue: Returns %true if a DMA flush queue is used > + * @dma_enable_flush_queue: Try to enable the DMA flush queue > * @domain_set_attr: Change domain attributes > * @get_resv_regions: Request list of reserved regions for a device > * @put_resv_regions: Free list of reserved regions for a device > @@ -244,8 +244,8 @@ struct iommu_ops { > void (*release_device)(struct device *dev); > void (*probe_finalize)(struct device *dev); > struct iommu_group *(*device_group)(struct device *dev); > - int (*domain_get_attr)(struct iommu_domain *domain, > - enum iommu_attr attr, void *data); > + bool (*dma_use_flush_queue)(struct iommu_domain *domain); > + void (*dma_enable_flush_queue)(struct iommu_domain *domain); > int (*domain_set_attr)(struct iommu_domain *domain, > enum iommu_attr attr, void *data); > > @@ -491,8 +491,7 @@ extern int iommu_page_response(struct device *dev, > extern int iommu_group_id(struct iommu_group *group); > extern struct iommu_domain *iommu_group_default_domain(struct iommu_group *); > > -extern int iommu_domain_get_attr(struct iommu_domain *domain, enum iommu_attr, > - void *data); > +bool iommu_dma_use_flush_queue(struct iommu_domain *domain); > extern int iommu_domain_set_attr(struct iommu_domain *domain, enum iommu_attr, > void *data); > > @@ -861,12 +860,6 @@ static inline int iommu_group_id(struct iommu_group *group) > return -ENODEV; > } > > -static inline int iommu_domain_get_attr(struct iommu_domain *domain, > - enum iommu_attr attr, void *data) > -{ > - return -EINVAL; > -} > - > static inline int iommu_domain_set_attr(struct iommu_domain *domain, > enum iommu_attr attr, void *data) > { >
On Thu, Mar 04, 2021 at 03:25:27PM +0000, Robin Murphy wrote: > On 2021-03-01 08:42, Christoph Hellwig wrote: >> Use explicit methods for setting and querying the information instead. > > Now that everyone's using iommu-dma, is there any point in bouncing this > through the drivers at all? Seems like it would make more sense for the x86 > drivers to reflect their private options back to iommu_dma_strict (and > allow Intel's caching mode to override it as well), then have > iommu_dma_init_domain just test !iommu_dma_strict && > domain->ops->flush_iotlb_all. Indeed. I switch to that.
On Thu, Mar 04, 2021 at 03:25:27PM +0000, Robin Murphy wrote: > On 2021-03-01 08:42, Christoph Hellwig wrote: >> Use explicit methods for setting and querying the information instead. > > Now that everyone's using iommu-dma, is there any point in bouncing this > through the drivers at all? Seems like it would make more sense for the x86 > drivers to reflect their private options back to iommu_dma_strict (and > allow Intel's caching mode to override it as well), then have > iommu_dma_init_domain just test !iommu_dma_strict && > domain->ops->flush_iotlb_all. Hmm. I looked at this, and kill off ->dma_enable_flush_queue for the ARM drivers and just looking at iommu_dma_strict seems like a very clear win. OTOH x86 is a little more complicated. AMD and intel defaul to lazy mode, so we'd have to change the global iommu_dma_strict if they are initialized. Also Intel has not only a "static" option to disable lazy mode, but also a "dynamic" one where it iterates structure. So I think on the get side we're stuck with the method, but it still simplifies the whole thing.
On Wed, Mar 10, 2021 at 10:15:01AM +0100, Christoph Hellwig wrote: > On Thu, Mar 04, 2021 at 03:25:27PM +0000, Robin Murphy wrote: > > On 2021-03-01 08:42, Christoph Hellwig wrote: > >> Use explicit methods for setting and querying the information instead. > > > > Now that everyone's using iommu-dma, is there any point in bouncing this > > through the drivers at all? Seems like it would make more sense for the x86 > > drivers to reflect their private options back to iommu_dma_strict (and > > allow Intel's caching mode to override it as well), then have > > iommu_dma_init_domain just test !iommu_dma_strict && > > domain->ops->flush_iotlb_all. > > Hmm. I looked at this, and kill off ->dma_enable_flush_queue for > the ARM drivers and just looking at iommu_dma_strict seems like a > very clear win. > > OTOH x86 is a little more complicated. AMD and intel defaul to lazy > mode, so we'd have to change the global iommu_dma_strict if they are > initialized. Also Intel has not only a "static" option to disable > lazy mode, but also a "dynamic" one where it iterates structure. So > I think on the get side we're stuck with the method, but it still > simplifies the whole thing. Actually... Just mirroring the iommu_dma_strict value into struct iommu_domain should solve all of that with very little boilerplate code.
On 2021-03-10 09:25, Christoph Hellwig wrote: > On Wed, Mar 10, 2021 at 10:15:01AM +0100, Christoph Hellwig wrote: >> On Thu, Mar 04, 2021 at 03:25:27PM +0000, Robin Murphy wrote: >>> On 2021-03-01 08:42, Christoph Hellwig wrote: >>>> Use explicit methods for setting and querying the information instead. >>> >>> Now that everyone's using iommu-dma, is there any point in bouncing this >>> through the drivers at all? Seems like it would make more sense for the x86 >>> drivers to reflect their private options back to iommu_dma_strict (and >>> allow Intel's caching mode to override it as well), then have >>> iommu_dma_init_domain just test !iommu_dma_strict && >>> domain->ops->flush_iotlb_all. >> >> Hmm. I looked at this, and kill off ->dma_enable_flush_queue for >> the ARM drivers and just looking at iommu_dma_strict seems like a >> very clear win. >> >> OTOH x86 is a little more complicated. AMD and intel defaul to lazy >> mode, so we'd have to change the global iommu_dma_strict if they are >> initialized. Also Intel has not only a "static" option to disable >> lazy mode, but also a "dynamic" one where it iterates structure. So >> I think on the get side we're stuck with the method, but it still >> simplifies the whole thing. > > Actually... Just mirroring the iommu_dma_strict value into > struct iommu_domain should solve all of that with very little > boilerplate code. Yes, my initial thought was to directly replace the attribute with a common flag at iommu_domain level, but since in all cases the behaviour is effectively global rather than actually per-domain, it seemed reasonable to take it a step further. This passes compile-testing for arm64 and x86, what do you think? Robin. ----->8----- Subject: [PATCH] iommu: Consolidate strict invalidation handling Now that everyone is using iommu-dma, the global invalidation policy really doesn't need to be woven through several parts of the core API and individual drivers, we can just look it up directly at the one point that we now make the flush queue decision. If the x86 drivers reflect their internal options and overrides back to iommu_dma_strict, that can become the canonical source. Signed-off-by: Robin Murphy <robin.murphy@arm.com> --- drivers/iommu/amd/iommu.c | 2 ++ drivers/iommu/dma-iommu.c | 8 +------- drivers/iommu/intel/iommu.c | 12 ++++++++++++ drivers/iommu/iommu.c | 35 +++++++++++++++++++++++++++-------- include/linux/iommu.h | 2 ++ 5 files changed, 44 insertions(+), 15 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index a69a8b573e40..1db29e59d468 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1856,6 +1856,8 @@ int __init amd_iommu_init_dma_ops(void) else pr_info("Lazy IO/TLB flushing enabled\n"); + iommu_set_dma_strict(amd_iommu_unmap_flush); + return 0; } diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index af765c813cc8..789a950cc125 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -304,10 +304,6 @@ static void iommu_dma_flush_iotlb_all(struct iova_domain *iovad) cookie = container_of(iovad, struct iommu_dma_cookie, iovad); domain = cookie->fq_domain; - /* - * The IOMMU driver supporting DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE - * implies that ops->flush_iotlb_all must be non-NULL. - */ domain->ops->flush_iotlb_all(domain); } @@ -334,7 +330,6 @@ static int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base, struct iommu_dma_cookie *cookie = domain->iova_cookie; unsigned long order, base_pfn; struct iova_domain *iovad; - int attr; if (!cookie || cookie->type != IOMMU_DMA_IOVA_COOKIE) return -EINVAL; @@ -371,8 +366,7 @@ static int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base, init_iova_domain(iovad, 1UL << order, base_pfn); if (!cookie->fq_domain && (!dev || !dev_is_untrusted(dev)) && - !iommu_domain_get_attr(domain, DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, &attr) && - attr) { + domain->ops->flush_iotlb_all && !iommu_get_dma_strict()) { if (init_iova_flush_queue(iovad, iommu_dma_flush_iotlb_all, iommu_dma_entry_dtor)) pr_warn("iova flush queue initialization failed\n"); diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index b5c746f0f63b..f5b452cd1266 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4377,6 +4377,17 @@ int __init intel_iommu_init(void) down_read(&dmar_global_lock); for_each_active_iommu(iommu, drhd) { + if (!intel_iommu_strict && cap_caching_mode(iommu->cap)) { + /* + * The flush queue implementation does not perform page-selective + * invalidations that are required for efficient TLB flushes in + * virtual environments. The benefit of batching is likely to be + * much lower than the overhead of synchronizing the virtual and + * physical IOMMU page-tables. + */ + pr_warn("IOMMU batching is disabled due to virtualization"); + intel_iommu_strict = 1; + } iommu_device_sysfs_add(&iommu->iommu, NULL, intel_iommu_groups, "%s", iommu->name); @@ -4384,6 +4395,7 @@ int __init intel_iommu_init(void) } up_read(&dmar_global_lock); + iommu_set_dma_strict(intel_iommu_strict); bus_set_iommu(&pci_bus_type, &intel_iommu_ops); if (si_domain && !hw_pass_through) register_memory_notifier(&intel_iommu_memory_nb); diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 2f3399203813..80afcf50cd3c 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -69,6 +69,7 @@ static const char * const iommu_group_resv_type_string[] = { }; #define IOMMU_CMD_LINE_DMA_API BIT(0) +#define IOMMU_CMD_LINE_STRICT BIT(1) static void iommu_set_cmd_line_dma_api(void) { @@ -80,6 +81,16 @@ static bool iommu_cmd_line_dma_api(void) return !!(iommu_cmd_line & IOMMU_CMD_LINE_DMA_API); } +static void iommu_set_cmd_line_strict(void) +{ + iommu_cmd_line |= IOMMU_CMD_LINE_STRICT; +} + +static bool iommu_cmd_line_strict(void) +{ + return !!(iommu_cmd_line & IOMMU_CMD_LINE_STRICT); +} + static int iommu_alloc_default_domain(struct iommu_group *group, struct device *dev); static struct iommu_domain *__iommu_domain_alloc(struct bus_type *bus, @@ -337,10 +348,25 @@ early_param("iommu.passthrough", iommu_set_def_domain_type); static int __init iommu_dma_setup(char *str) { - return kstrtobool(str, &iommu_dma_strict); + int ret = kstrtobool(str, &iommu_dma_strict); + + if (!ret) + iommu_set_cmd_line_strict(); + return ret; } early_param("iommu.strict", iommu_dma_setup); +void iommu_set_dma_strict(bool val) +{ + if (val || !iommu_cmd_line_strict()) + iommu_dma_strict = val; +} + +bool iommu_get_dma_strict(void) +{ + return iommu_dma_strict; +} + static ssize_t iommu_group_attr_show(struct kobject *kobj, struct attribute *__attr, char *buf) { @@ -1520,13 +1546,6 @@ static int iommu_group_alloc_default_domain(struct bus_type *bus, if (!group->domain) group->domain = dom; - if (!iommu_dma_strict) { - int attr = 1; - iommu_domain_set_attr(dom, - DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, - &attr); - } - return 0; } diff --git a/include/linux/iommu.h b/include/linux/iommu.h index eb5e3f14c5ad..11bbfa273d98 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -495,6 +495,8 @@ extern int iommu_domain_get_attr(struct iommu_domain *domain, enum iommu_attr, void *data); extern int iommu_domain_set_attr(struct iommu_domain *domain, enum iommu_attr, void *data); +extern void iommu_set_dma_strict(bool val); +extern bool iommu_get_dma_strict(void); /* Window handling function prototypes */ extern int iommu_domain_window_enable(struct iommu_domain *domain, u32 wnd_nr,
On Wed, Mar 10, 2021 at 06:39:57PM +0000, Robin Murphy wrote: >> Actually... Just mirroring the iommu_dma_strict value into >> struct iommu_domain should solve all of that with very little >> boilerplate code. > > Yes, my initial thought was to directly replace the attribute with a > common flag at iommu_domain level, but since in all cases the behaviour > is effectively global rather than actually per-domain, it seemed > reasonable to take it a step further. This passes compile-testing for > arm64 and x86, what do you think? It seems to miss a few bits, and also generally seems to be not actually apply to recent mainline or something like it due to different empty lines in a few places. Let me know what you think of the version here: http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/iommu-cleanup I'll happily switch the patch to you as the author if you're fine with that as well.
On 2021-03-11 08:26, Christoph Hellwig wrote: > On Wed, Mar 10, 2021 at 06:39:57PM +0000, Robin Murphy wrote: >>> Actually... Just mirroring the iommu_dma_strict value into >>> struct iommu_domain should solve all of that with very little >>> boilerplate code. >> >> Yes, my initial thought was to directly replace the attribute with a >> common flag at iommu_domain level, but since in all cases the behaviour >> is effectively global rather than actually per-domain, it seemed >> reasonable to take it a step further. This passes compile-testing for >> arm64 and x86, what do you think? > > It seems to miss a few bits, and also generally seems to be not actually > apply to recent mainline or something like it due to different empty > lines in a few places. Yeah, that was sketched out on top of some other development patches, and in being so focused on not breaking any of the x86 behaviours I did indeed overlook fully converting the SMMU drivers... oops! (my thought was to do the conversion for its own sake, then clean up the redundant attribute separately, but I guess it's fine either way) > Let me know what you think of the version here: > > http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/iommu-cleanup > > I'll happily switch the patch to you as the author if you're fine with > that as well. I still have reservations about removing the attribute API entirely and pretending that io_pgtable_cfg is anything other than a SoC-specific private interface, but the reworked patch on its own looks reasonable to me, thanks! (I wasn't too convinced about the iommu_cmd_line wrappers either...) Just iommu_get_dma_strict() needs an export since the SMMU drivers can be modular - I consciously didn't add that myself since I was mistakenly thinking only iommu-dma would call it. Robin.
On Fri, Mar 12, 2021 at 04:18:24PM +0000, Robin Murphy wrote: >> Let me know what you think of the version here: >> >> http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/iommu-cleanup >> >> I'll happily switch the patch to you as the author if you're fine with >> that as well. > > I still have reservations about removing the attribute API entirely and > pretending that io_pgtable_cfg is anything other than a SoC-specific > private interface, I think a private inteface would make more sense. For now I've just condensed it down to a generic set of quirk bits and dropped the attrs structure, which seems like an ok middle ground for now. That being said I wonder why that quirk isn't simply set in the device tree? > but the reworked patch on its own looks reasonable to > me, thanks! (I wasn't too convinced about the iommu_cmd_line wrappers > either...) Just iommu_get_dma_strict() needs an export since the SMMU > drivers can be modular - I consciously didn't add that myself since I was > mistakenly thinking only iommu-dma would call it. Fixed. Can I get your signoff for the patch? Then I'll switch it to over to being attributed to you.
On 2021-03-15 08:33, Christoph Hellwig wrote: > On Fri, Mar 12, 2021 at 04:18:24PM +0000, Robin Murphy wrote: >>> Let me know what you think of the version here: >>> >>> http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/iommu-cleanup >>> >>> I'll happily switch the patch to you as the author if you're fine with >>> that as well. >> >> I still have reservations about removing the attribute API entirely and >> pretending that io_pgtable_cfg is anything other than a SoC-specific >> private interface, > > I think a private inteface would make more sense. For now I've just > condensed it down to a generic set of quirk bits and dropped the > attrs structure, which seems like an ok middle ground for now. That > being said I wonder why that quirk isn't simply set in the device > tree? Because it's a software policy decision rather than any inherent property of the platform, and the DT certainly doesn't know *when* any particular device might prefer its IOMMU to use cacheable pagetables to minimise TLB miss latency vs. saving the cache capacity for larger data buffers. It really is most logical to decide this at the driver level. In truth the overall concept *is* relatively generic (a trend towards larger system caches and cleverer usage is about both raw performance and saving power on off-SoC DRAM traffic), it's just the particular implementation of using io-pgtable to set an outer-cacheable walk attribute in an SMMU TCR that's pretty much specific to Qualcomm SoCs. Hence why having a common abstraction at the iommu_domain level, but where the exact details are free to vary across different IOMMUs and their respective client drivers, is in many ways an ideal fit. >> but the reworked patch on its own looks reasonable to >> me, thanks! (I wasn't too convinced about the iommu_cmd_line wrappers >> either...) Just iommu_get_dma_strict() needs an export since the SMMU >> drivers can be modular - I consciously didn't add that myself since I was >> mistakenly thinking only iommu-dma would call it. > > Fixed. Can I get your signoff for the patch? Then I'll switch it to > over to being attributed to you. Sure - I would have thought that the one I originally posted still stands, but for the avoidance of doubt, for the parts of commit 8b6d45c495bd in your tree that remain from what I wrote: Signed-off-by: Robin Murphy <robin.murphy@arm.com> Cheers, Robin.
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index a69a8b573e40d0..37a8e51db17656 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1771,24 +1771,11 @@ static struct iommu_group *amd_iommu_device_group(struct device *dev) return acpihid_device_group(dev); } -static int amd_iommu_domain_get_attr(struct iommu_domain *domain, - enum iommu_attr attr, void *data) +static bool amd_iommu_dma_use_flush_queue(struct iommu_domain *domain) { - switch (domain->type) { - case IOMMU_DOMAIN_UNMANAGED: - return -ENODEV; - case IOMMU_DOMAIN_DMA: - switch (attr) { - case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE: - *(int *)data = !amd_iommu_unmap_flush; - return 0; - default: - return -ENODEV; - } - break; - default: - return -EINVAL; - } + if (domain->type != IOMMU_DOMAIN_DMA) + return false; + return !amd_iommu_unmap_flush; } /***************************************************************************** @@ -2257,7 +2244,7 @@ const struct iommu_ops amd_iommu_ops = { .release_device = amd_iommu_release_device, .probe_finalize = amd_iommu_probe_finalize, .device_group = amd_iommu_device_group, - .domain_get_attr = amd_iommu_domain_get_attr, + .dma_use_flush_queue = amd_iommu_dma_use_flush_queue, .get_resv_regions = amd_iommu_get_resv_regions, .put_resv_regions = generic_iommu_put_resv_regions, .is_attach_deferred = amd_iommu_is_attach_deferred, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 8594b4a8304375..bf96172e8c1f71 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2449,33 +2449,21 @@ static struct iommu_group *arm_smmu_device_group(struct device *dev) return group; } -static int arm_smmu_domain_get_attr(struct iommu_domain *domain, - enum iommu_attr attr, void *data) +static bool arm_smmu_dma_use_flush_queue(struct iommu_domain *domain) { struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); - switch (domain->type) { - case IOMMU_DOMAIN_UNMANAGED: - switch (attr) { - case DOMAIN_ATTR_NESTING: - *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED); - return 0; - default: - return -ENODEV; - } - break; - case IOMMU_DOMAIN_DMA: - switch (attr) { - case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE: - *(int *)data = smmu_domain->non_strict; - return 0; - default: - return -ENODEV; - } - break; - default: - return -EINVAL; - } + if (domain->type != IOMMU_DOMAIN_DMA) + return false; + return smmu_domain->non_strict; +} + + +static void arm_smmu_dma_enable_flush_queue(struct iommu_domain *domain) +{ + if (domain->type != IOMMU_DOMAIN_DMA) + return; + to_smmu_domain(domain)->non_strict = true; } static int arm_smmu_domain_set_attr(struct iommu_domain *domain, @@ -2505,13 +2493,7 @@ static int arm_smmu_domain_set_attr(struct iommu_domain *domain, } break; case IOMMU_DOMAIN_DMA: - switch(attr) { - case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE: - smmu_domain->non_strict = *(int *)data; - break; - default: - ret = -ENODEV; - } + ret = -ENODEV; break; default: ret = -EINVAL; @@ -2619,7 +2601,8 @@ static struct iommu_ops arm_smmu_ops = { .probe_device = arm_smmu_probe_device, .release_device = arm_smmu_release_device, .device_group = arm_smmu_device_group, - .domain_get_attr = arm_smmu_domain_get_attr, + .dma_use_flush_queue = arm_smmu_dma_use_flush_queue, + .dma_enable_flush_queue = arm_smmu_dma_enable_flush_queue, .domain_set_attr = arm_smmu_domain_set_attr, .of_xlate = arm_smmu_of_xlate, .get_resv_regions = arm_smmu_get_resv_regions, diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index d8c6bfde6a6158..e7893e96f5177a 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1481,42 +1481,20 @@ static struct iommu_group *arm_smmu_device_group(struct device *dev) return group; } -static int arm_smmu_domain_get_attr(struct iommu_domain *domain, - enum iommu_attr attr, void *data) +static bool arm_smmu_dma_use_flush_queue(struct iommu_domain *domain) { struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); - switch(domain->type) { - case IOMMU_DOMAIN_UNMANAGED: - switch (attr) { - case DOMAIN_ATTR_NESTING: - *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED); - return 0; - case DOMAIN_ATTR_IO_PGTABLE_CFG: { - struct io_pgtable_domain_attr *pgtbl_cfg = data; - *pgtbl_cfg = smmu_domain->pgtbl_cfg; + if (domain->type != IOMMU_DOMAIN_DMA) + return false; + return smmu_domain->pgtbl_cfg.quirks & IO_PGTABLE_QUIRK_NON_STRICT; +} - return 0; - } - default: - return -ENODEV; - } - break; - case IOMMU_DOMAIN_DMA: - switch (attr) { - case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE: { - bool non_strict = smmu_domain->pgtbl_cfg.quirks & - IO_PGTABLE_QUIRK_NON_STRICT; - *(int *)data = non_strict; - return 0; - } - default: - return -ENODEV; - } - break; - default: - return -EINVAL; - } +static void arm_smmu_dma_enable_flush_queue(struct iommu_domain *domain) +{ + if (domain->type != IOMMU_DOMAIN_DMA) + return; + to_smmu_domain(domain)->pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT; } static int arm_smmu_domain_set_attr(struct iommu_domain *domain, @@ -1557,16 +1535,7 @@ static int arm_smmu_domain_set_attr(struct iommu_domain *domain, } break; case IOMMU_DOMAIN_DMA: - switch (attr) { - case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE: - if (*(int *)data) - smmu_domain->pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT; - else - smmu_domain->pgtbl_cfg.quirks &= ~IO_PGTABLE_QUIRK_NON_STRICT; - break; - default: - ret = -ENODEV; - } + ret = -ENODEV; break; default: ret = -EINVAL; @@ -1631,7 +1600,8 @@ static struct iommu_ops arm_smmu_ops = { .probe_device = arm_smmu_probe_device, .release_device = arm_smmu_release_device, .device_group = arm_smmu_device_group, - .domain_get_attr = arm_smmu_domain_get_attr, + .dma_use_flush_queue = arm_smmu_dma_use_flush_queue, + .dma_enable_flush_queue = arm_smmu_dma_enable_flush_queue, .domain_set_attr = arm_smmu_domain_set_attr, .of_xlate = arm_smmu_of_xlate, .get_resv_regions = arm_smmu_get_resv_regions, diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 9ab6ee22c11088..d3fe5aad9d6ecf 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -305,8 +305,8 @@ static void iommu_dma_flush_iotlb_all(struct iova_domain *iovad) cookie = container_of(iovad, struct iommu_dma_cookie, iovad); domain = cookie->fq_domain; /* - * The IOMMU driver supporting DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE - * implies that ops->flush_iotlb_all must be non-NULL. + * The IOMMU driver supporting a DMA flush queue implies that + * ops->flush_iotlb_all must be non-NULL. */ domain->ops->flush_iotlb_all(domain); } @@ -329,7 +329,6 @@ static int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base, struct iommu_dma_cookie *cookie = domain->iova_cookie; unsigned long order, base_pfn; struct iova_domain *iovad; - int attr; if (!cookie || cookie->type != IOMMU_DMA_IOVA_COOKIE) return -EINVAL; @@ -365,8 +364,7 @@ static int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base, init_iova_domain(iovad, 1UL << order, base_pfn); - if (!cookie->fq_domain && !iommu_domain_get_attr(domain, - DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, &attr) && attr) { + if (!cookie->fq_domain && iommu_dma_use_flush_queue(domain)) { if (init_iova_flush_queue(iovad, iommu_dma_flush_iotlb_all, iommu_dma_entry_dtor)) pr_warn("iova flush queue initialization failed\n"); diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index ee0932307d646b..eaa80c33f4bc91 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -5453,13 +5453,13 @@ intel_iommu_domain_set_attr(struct iommu_domain *domain, return ret; } -static bool domain_use_flush_queue(void) +static bool intel_iommu_dma_use_flush_queue(struct iommu_domain *domain) { struct dmar_drhd_unit *drhd; struct intel_iommu *iommu; bool r = true; - if (intel_iommu_strict) + if (domain->type != IOMMU_DOMAIN_DMA || intel_iommu_strict) return false; /* @@ -5483,27 +5483,6 @@ static bool domain_use_flush_queue(void) return r; } -static int -intel_iommu_domain_get_attr(struct iommu_domain *domain, - enum iommu_attr attr, void *data) -{ - switch (domain->type) { - case IOMMU_DOMAIN_UNMANAGED: - return -ENODEV; - case IOMMU_DOMAIN_DMA: - switch (attr) { - case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE: - *(int *)data = domain_use_flush_queue(); - return 0; - default: - return -ENODEV; - } - break; - default: - return -EINVAL; - } -} - /* * Check that the device does not live on an external facing PCI port that is * marked as untrusted. Such devices should not be able to apply quirks and @@ -5576,7 +5555,7 @@ const struct iommu_ops intel_iommu_ops = { .capable = intel_iommu_capable, .domain_alloc = intel_iommu_domain_alloc, .domain_free = intel_iommu_domain_free, - .domain_get_attr = intel_iommu_domain_get_attr, + .dma_use_flush_queue = intel_iommu_dma_use_flush_queue, .domain_set_attr = intel_iommu_domain_set_attr, .attach_dev = intel_iommu_attach_device, .detach_dev = intel_iommu_detach_device, diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 23daaea7883b75..0f12c4d58cdc42 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -1512,12 +1512,8 @@ static int iommu_group_alloc_default_domain(struct bus_type *bus, if (!group->domain) group->domain = dom; - if (!iommu_dma_strict) { - int attr = 1; - iommu_domain_set_attr(dom, - DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, - &attr); - } + if (!iommu_dma_strict && dom->ops->dma_enable_flush_queue) + dom->ops->dma_enable_flush_queue(dom); return 0; } @@ -2664,14 +2660,13 @@ static int __init iommu_init(void) } core_initcall(iommu_init); -int iommu_domain_get_attr(struct iommu_domain *domain, - enum iommu_attr attr, void *data) +bool iommu_dma_use_flush_queue(struct iommu_domain *domain) { - if (!domain->ops->domain_get_attr) - return -EINVAL; - return domain->ops->domain_get_attr(domain, attr, data); + if (!domain->ops->dma_use_flush_queue) + return false; + return domain->ops->dma_use_flush_queue(domain); } -EXPORT_SYMBOL_GPL(iommu_domain_get_attr); +EXPORT_SYMBOL_GPL(iommu_dma_use_flush_queue); int iommu_domain_set_attr(struct iommu_domain *domain, enum iommu_attr attr, void *data) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index c15a8658daad64..f30de33c6ff56e 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -108,7 +108,6 @@ enum iommu_cap { enum iommu_attr { DOMAIN_ATTR_NESTING, /* two stages of translation */ - DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, DOMAIN_ATTR_IO_PGTABLE_CFG, DOMAIN_ATTR_MAX, }; @@ -194,7 +193,8 @@ struct iommu_iotlb_gather { * @probe_finalize: Do final setup work after the device is added to an IOMMU * group and attached to the groups domain * @device_group: find iommu group for a particular device - * @domain_get_attr: Query domain attributes + * @dma_use_flush_queue: Returns %true if a DMA flush queue is used + * @dma_enable_flush_queue: Try to enable the DMA flush queue * @domain_set_attr: Change domain attributes * @get_resv_regions: Request list of reserved regions for a device * @put_resv_regions: Free list of reserved regions for a device @@ -244,8 +244,8 @@ struct iommu_ops { void (*release_device)(struct device *dev); void (*probe_finalize)(struct device *dev); struct iommu_group *(*device_group)(struct device *dev); - int (*domain_get_attr)(struct iommu_domain *domain, - enum iommu_attr attr, void *data); + bool (*dma_use_flush_queue)(struct iommu_domain *domain); + void (*dma_enable_flush_queue)(struct iommu_domain *domain); int (*domain_set_attr)(struct iommu_domain *domain, enum iommu_attr attr, void *data); @@ -491,8 +491,7 @@ extern int iommu_page_response(struct device *dev, extern int iommu_group_id(struct iommu_group *group); extern struct iommu_domain *iommu_group_default_domain(struct iommu_group *); -extern int iommu_domain_get_attr(struct iommu_domain *domain, enum iommu_attr, - void *data); +bool iommu_dma_use_flush_queue(struct iommu_domain *domain); extern int iommu_domain_set_attr(struct iommu_domain *domain, enum iommu_attr, void *data); @@ -861,12 +860,6 @@ static inline int iommu_group_id(struct iommu_group *group) return -ENODEV; } -static inline int iommu_domain_get_attr(struct iommu_domain *domain, - enum iommu_attr attr, void *data) -{ - return -EINVAL; -} - static inline int iommu_domain_set_attr(struct iommu_domain *domain, enum iommu_attr attr, void *data) {
Use explicit methods for setting and querying the information instead. Also remove the now unused iommu_domain_get_attr functionality. Signed-off-by: Christoph Hellwig <hch@lst.de> --- drivers/iommu/amd/iommu.c | 23 ++------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 47 ++++++----------- drivers/iommu/arm/arm-smmu/arm-smmu.c | 56 +++++---------------- drivers/iommu/dma-iommu.c | 8 ++- drivers/iommu/intel/iommu.c | 27 ++-------- drivers/iommu/iommu.c | 19 +++---- include/linux/iommu.h | 17 ++----- 7 files changed, 51 insertions(+), 146 deletions(-)