| Message ID | ddafbffafe48fc55bed050728e2ce2610c934e7b.1615221459.git.cristian.ciocaltea@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Improve clock support for Actions S500 SoC | expand |
On Mon, Mar 08, 2021 at 07:18:31PM +0200, Cristian Ciocaltea wrote: > Add support for the missing NIC and ETHERNET clocks in the Actions Semi > Owl S500 SoC clock driver. > > Additionally, change APB clock parent from AHB to the newly added NIC. > > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> > --- > drivers/clk/actions/owl-s500.c | 17 ++++++++++++++++- > 1 file changed, 16 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c > index b9e434173b4f..0ccc9619b302 100644 > --- a/drivers/clk/actions/owl-s500.c > +++ b/drivers/clk/actions/owl-s500.c > @@ -112,6 +112,7 @@ static const char * const bisp_clk_mux_p[] = { "display_pll_clk", "dev_clk" }; > static const char * const sensor_clk_mux_p[] = { "hosc", "bisp_clk" }; > static const char * const sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk" }; > static const char * const pwm_clk_mux_p[] = { "losc", "hosc" }; > +static const char * const nic_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" }; As per the reg field order, this should come after "ahbprediv_clk_mux_p" Rest looks good. Thanks, Mani > static const char * const ahbprediv_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" }; > static const char * const uart_clk_mux_p[] = { "hosc", "dev_pll_clk" }; > static const char * const de_clk_mux_p[] = { "display_pll_clk", "dev_clk" }; > @@ -197,7 +198,7 @@ static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0); > > /* divider clocks */ > static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 2, 2, h_div_table, 0, 0); > -static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0); > +static OWL_DIVIDER(apb_clk, "apb_clk", "nic_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0); > static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0); > > /* factor clocks */ > @@ -205,6 +206,12 @@ static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table > static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0); > > /* composite clocks */ > +static OWL_COMP_DIV(nic_clk, "nic_clk", nic_clk_mux_p, > + OWL_MUX_HW(CMU_BUSCLK1, 4, 3), > + { 0 }, > + OWL_DIVIDER_HW(CMU_BUSCLK1, 16, 2, 0, NULL), > + 0); > + > static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, > OWL_MUX_HW(CMU_BUSCLK1, 8, 3), > { 0 }, > @@ -320,6 +327,10 @@ static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk", > OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0), > 1, 5, 0); > > +static OWL_COMP_FIXED_FACTOR(ethernet_clk, "ethernet_clk", "ethernet_pll_clk", > + OWL_GATE_HW(CMU_DEVCLKEN1, 22, 0), > + 1, 20, 0); > + > static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p, > OWL_MUX_HW(CMU_UART0CLK, 16, 1), > OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0), > @@ -454,6 +465,8 @@ static struct owl_clk_common *s500_clks[] = { > &apb_clk.common, > &dmac_clk.common, > &gpio_clk.common, > + &nic_clk.common, > + ðernet_clk.common, > }; > > static struct clk_hw_onecell_data s500_hw_clks = { > @@ -513,6 +526,8 @@ static struct clk_hw_onecell_data s500_hw_clks = { > [CLK_APB] = &apb_clk.common.hw, > [CLK_DMAC] = &dmac_clk.common.hw, > [CLK_GPIO] = &gpio_clk.common.hw, > + [CLK_NIC] = &nic_clk.common.hw, > + [CLK_ETHERNET] = ðernet_clk.common.hw, > }, > .num = CLK_NR_CLKS, > }; > -- > 2.30.1 >
On Tue, Mar 16, 2021 at 11:22:40AM +0530, Manivannan Sadhasivam wrote: > On Mon, Mar 08, 2021 at 07:18:31PM +0200, Cristian Ciocaltea wrote: > > Add support for the missing NIC and ETHERNET clocks in the Actions Semi > > Owl S500 SoC clock driver. > > > > Additionally, change APB clock parent from AHB to the newly added NIC. > > > > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> > > --- > > drivers/clk/actions/owl-s500.c | 17 ++++++++++++++++- > > 1 file changed, 16 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c > > index b9e434173b4f..0ccc9619b302 100644 > > --- a/drivers/clk/actions/owl-s500.c > > +++ b/drivers/clk/actions/owl-s500.c > > @@ -112,6 +112,7 @@ static const char * const bisp_clk_mux_p[] = { "display_pll_clk", "dev_clk" }; > > static const char * const sensor_clk_mux_p[] = { "hosc", "bisp_clk" }; > > static const char * const sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk" }; > > static const char * const pwm_clk_mux_p[] = { "losc", "hosc" }; > > +static const char * const nic_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" }; > > As per the reg field order, this should come after "ahbprediv_clk_mux_p" Fixed, thanks! > Rest looks good. > > Thanks, > Mani > [...]
diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c index b9e434173b4f..0ccc9619b302 100644 --- a/drivers/clk/actions/owl-s500.c +++ b/drivers/clk/actions/owl-s500.c @@ -112,6 +112,7 @@ static const char * const bisp_clk_mux_p[] = { "display_pll_clk", "dev_clk" }; static const char * const sensor_clk_mux_p[] = { "hosc", "bisp_clk" }; static const char * const sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk" }; static const char * const pwm_clk_mux_p[] = { "losc", "hosc" }; +static const char * const nic_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" }; static const char * const ahbprediv_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" }; static const char * const uart_clk_mux_p[] = { "hosc", "dev_pll_clk" }; static const char * const de_clk_mux_p[] = { "display_pll_clk", "dev_clk" }; @@ -197,7 +198,7 @@ static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0); /* divider clocks */ static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 2, 2, h_div_table, 0, 0); -static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0); +static OWL_DIVIDER(apb_clk, "apb_clk", "nic_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0); static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0); /* factor clocks */ @@ -205,6 +206,12 @@ static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0); /* composite clocks */ +static OWL_COMP_DIV(nic_clk, "nic_clk", nic_clk_mux_p, + OWL_MUX_HW(CMU_BUSCLK1, 4, 3), + { 0 }, + OWL_DIVIDER_HW(CMU_BUSCLK1, 16, 2, 0, NULL), + 0); + static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, OWL_MUX_HW(CMU_BUSCLK1, 8, 3), { 0 }, @@ -320,6 +327,10 @@ static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk", OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0), 1, 5, 0); +static OWL_COMP_FIXED_FACTOR(ethernet_clk, "ethernet_clk", "ethernet_pll_clk", + OWL_GATE_HW(CMU_DEVCLKEN1, 22, 0), + 1, 20, 0); + static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART0CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0), @@ -454,6 +465,8 @@ static struct owl_clk_common *s500_clks[] = { &apb_clk.common, &dmac_clk.common, &gpio_clk.common, + &nic_clk.common, + ðernet_clk.common, }; static struct clk_hw_onecell_data s500_hw_clks = { @@ -513,6 +526,8 @@ static struct clk_hw_onecell_data s500_hw_clks = { [CLK_APB] = &apb_clk.common.hw, [CLK_DMAC] = &dmac_clk.common.hw, [CLK_GPIO] = &gpio_clk.common.hw, + [CLK_NIC] = &nic_clk.common.hw, + [CLK_ETHERNET] = ðernet_clk.common.hw, }, .num = CLK_NR_CLKS, };
Add support for the missing NIC and ETHERNET clocks in the Actions Semi Owl S500 SoC clock driver. Additionally, change APB clock parent from AHB to the newly added NIC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> --- drivers/clk/actions/owl-s500.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-)