| Message ID | 1616410796-43167-1-git-send-email-robert.hu@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | i386/cpu_dump: support AVX512 ZMM regs dump | expand |
On 3/22/21 4:59 AM, Robert Hoo wrote: > Since commit fa4518741e (target-i386: Rename struct XMMReg to ZMMReg), > CPUX86State.xmm_regs[] has already been extended to 512bit to support > AVX512. > Also, other qemu level supports for AVX512 registers are there for > years. > But in x86_cpu_dump_state(), still only dump XMM registers. > This patch is just to complement this part, let it dump ZMM of 512bits. I think you should examine the state of the cpu to determine what of SSE, AVX or AVX512 is currently enabled, then dump that. > - if (env->hflags & HF_CS64_MASK) > - nb = 16; > - else > - nb = 8; > - for(i=0;i<nb;i++) { > - qemu_fprintf(f, "XMM%02d=%08x%08x%08x%08x", > + > + nb = sizeof(env->xmm_regs) / sizeof(env->xmm_regs[0]); E.g., you're dumping all of the registers in 32-bit mode, which is restricted to 8 registers, not 32. r~
On Mon, 2021-03-22 at 15:06 -0600, Richard Henderson wrote: > On 3/22/21 4:59 AM, Robert Hoo wrote: > > Since commit fa4518741e (target-i386: Rename struct XMMReg to > > ZMMReg), > > CPUX86State.xmm_regs[] has already been extended to 512bit to > > support > > AVX512. > > Also, other qemu level supports for AVX512 registers are there for > > years. > > But in x86_cpu_dump_state(), still only dump XMM registers. > > This patch is just to complement this part, let it dump ZMM of > > 512bits. > > I think you should examine the state of the cpu to determine what of > SSE, AVX > or AVX512 is currently enabled, then dump that. Thanks Richard for review. Uh, looks like the existing code doesn't have this logic yet. OK, I'm to add this logic. > > > - if (env->hflags & HF_CS64_MASK) > > - nb = 16; > > - else > > - nb = 8; > > - for(i=0;i<nb;i++) { > > - qemu_fprintf(f, "XMM%02d=%08x%08x%08x%08x", > > + > > + nb = sizeof(env->xmm_regs) / sizeof(env->xmm_regs[0]); > > E.g., you're dumping all of the registers in 32-bit mode, which is > restricted > to 8 registers, not 32. In typedef struct CPUX86State { ... ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; ... } where in cpu.h #define CPU_NB_REGS64 16 #define CPU_NB_REGS32 8 #ifdef TARGET_X86_64 #define CPU_NB_REGS CPU_NB_REGS64 #else #define CPU_NB_REGS CPU_NB_REGS32 #endif so the register number is 8 in 32-bit mode and 32 in 64-bit mode. > > > r~
On 3/23/21 1:00 AM, Robert Hoo wrote: > On Mon, 2021-03-22 at 15:06 -0600, Richard Henderson wrote: >> On 3/22/21 4:59 AM, Robert Hoo wrote: >>> Since commit fa4518741e (target-i386: Rename struct XMMReg to >>> ZMMReg), >>> CPUX86State.xmm_regs[] has already been extended to 512bit to >>> support >>> AVX512. >>> Also, other qemu level supports for AVX512 registers are there for >>> years. >>> But in x86_cpu_dump_state(), still only dump XMM registers. >>> This patch is just to complement this part, let it dump ZMM of >>> 512bits. >> >> I think you should examine the state of the cpu to determine what of >> SSE, AVX >> or AVX512 is currently enabled, then dump that. > > Thanks Richard for review. > > Uh, looks like the existing code doesn't have this logic yet. > OK, I'm to add this logic. Correct. >>> - if (env->hflags & HF_CS64_MASK) >>> - nb = 16; >>> - else >>> - nb = 8; >>> - for(i=0;i<nb;i++) { >>> - qemu_fprintf(f, "XMM%02d=%08x%08x%08x%08x", >>> + >>> + nb = sizeof(env->xmm_regs) / sizeof(env->xmm_regs[0]); >> >> E.g., you're dumping all of the registers in 32-bit mode, which is >> restricted >> to 8 registers, not 32. > > In typedef struct CPUX86State { > ... > ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; > ... > } > > where in cpu.h > > #define CPU_NB_REGS64 16 > #define CPU_NB_REGS32 8 > > #ifdef TARGET_X86_64 > #define CPU_NB_REGS CPU_NB_REGS64 > #else > #define CPU_NB_REGS CPU_NB_REGS32 > #endif > > so the register number is 8 in 32-bit mode and 32 in 64-bit mode. The array size is the maximum. But of course a 64-bit cpu can be put into 32-bit mode. You removed the exact check for that, using HF_CS64_MASK, quoted above. r~
diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c index aac21f1..789e774 100644 --- a/target/i386/cpu-dump.c +++ b/target/i386/cpu-dump.c @@ -499,17 +499,20 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags) else qemu_fprintf(f, " "); } - if (env->hflags & HF_CS64_MASK) - nb = 16; - else - nb = 8; - for(i=0;i<nb;i++) { - qemu_fprintf(f, "XMM%02d=%08x%08x%08x%08x", + + nb = sizeof(env->xmm_regs) / sizeof(env->xmm_regs[0]); + for (i = 0; i < nb; i++) { + qemu_fprintf(f, "ZMM%02d=0x%016lx %016lx %016lx %016lx %016lx " + "%016lx %016lx %016lx", i, - env->xmm_regs[i].ZMM_L(3), - env->xmm_regs[i].ZMM_L(2), - env->xmm_regs[i].ZMM_L(1), - env->xmm_regs[i].ZMM_L(0)); + env->xmm_regs[i].ZMM_Q(7), + env->xmm_regs[i].ZMM_Q(6), + env->xmm_regs[i].ZMM_Q(5), + env->xmm_regs[i].ZMM_Q(4), + env->xmm_regs[i].ZMM_Q(3), + env->xmm_regs[i].ZMM_Q(2), + env->xmm_regs[i].ZMM_Q(1), + env->xmm_regs[i].ZMM_Q(0)); if ((i & 1) == 1) qemu_fprintf(f, "\n"); else
Since commit fa4518741e (target-i386: Rename struct XMMReg to ZMMReg), CPUX86State.xmm_regs[] has already been extended to 512bit to support AVX512. Also, other qemu level supports for AVX512 registers are there for years. But in x86_cpu_dump_state(), still only dump XMM registers. This patch is just to complement this part, let it dump ZMM of 512bits. Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> --- target/i386/cpu-dump.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-)