| Message ID | 20210324165023.32352-5-kabel@kernel.org (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | net: phy: marvell10g updates | expand |
| Context | Check | Description |
|---|---|---|
| netdev/cover_letter | success | Link |
| netdev/fixes_present | success | Link |
| netdev/patch_count | success | Link |
| netdev/tree_selection | success | Clearly marked for net-next |
| netdev/subject_prefix | success | Link |
| netdev/cc_maintainers | warning | 1 maintainers not CCed: linux@armlinux.org.uk |
| netdev/source_inline | success | Was 0 now: 0 |
| netdev/verify_signedoff | success | Link |
| netdev/module_param | success | Was 0 now: 0 |
| netdev/build_32bit | success | Errors and warnings before: 0 this patch: 0 |
| netdev/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| netdev/verify_fixes | success | Link |
| netdev/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 25 lines checked |
| netdev/build_allmodconfig_warn | success | Errors and warnings before: 0 this patch: 0 |
| netdev/header_inline | success | Link |
On Wed, Mar 24, 2021 at 05:50:20PM +0100, Marek Behún wrote: > Add all MACTYPE definitions for 88X3310/88X3310P. > > In order to have consistent naming, rename > MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH to > MV_V2_PORT_CTRL_MACTYPE_10GR_RATE_MATCH. We probably ought to note that the 88x3310 and 88x3340 will be detected by this driver, but have different MACTYPE definitions.
On Wed, 24 Mar 2021 16:58:36 +0000 Russell King - ARM Linux admin <linux@armlinux.org.uk> wrote: > On Wed, Mar 24, 2021 at 05:50:20PM +0100, Marek Behún wrote: > > Add all MACTYPE definitions for 88X3310/88X3310P. > > > > In order to have consistent naming, rename > > MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH to > > MV_V2_PORT_CTRL_MACTYPE_10GR_RATE_MATCH. > > We probably ought to note that the 88x3310 and 88x3340 will be detected > by this driver, but have different MACTYPE definitions. Is 88X3340 supported? The drivers structure only defines for .phy_id = MARVELL_PHY_ID_88X3310 Do 88X3310 and 3340 have the same PHY_ID ? Also these registers are different for 88E2110, and the register which contains MACTYPE has a different address. Yes, I want to do this, but in another series, because I don't have the board with 88E2210 now. Marek
On Wed, Mar 24, 2021 at 06:09:09PM +0000, Marek Behún wrote: > On Wed, 24 Mar 2021 16:58:36 +0000 > Russell King - ARM Linux admin <linux@armlinux.org.uk> wrote: > > > On Wed, Mar 24, 2021 at 05:50:20PM +0100, Marek Behún wrote: > > > Add all MACTYPE definitions for 88X3310/88X3310P. > > > > > > In order to have consistent naming, rename > > > MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH to > > > MV_V2_PORT_CTRL_MACTYPE_10GR_RATE_MATCH. > > > > We probably ought to note that the 88x3310 and 88x3340 will be detected > > by this driver, but have different MACTYPE definitions. > > Is 88X3340 supported? The drivers structure only defines for > .phy_id = MARVELL_PHY_ID_88X3310 > Do 88X3310 and 3340 have the same PHY_ID ? Yes they do. I believe they can be distinguished by bit 3, conventionally part of the PHY revision.
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c index 70639b9393f3..46e853f2d41b 100644 --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c @@ -80,8 +80,15 @@ enum { MV_V2_PORT_CTRL = 0xf001, MV_V2_PORT_CTRL_SWRST = BIT(15), MV_V2_PORT_CTRL_PWRDOWN = BIT(11), - MV_V2_PORT_CTRL_MACTYPE_MASK = 0x7, - MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6, + MV_V2_PORT_CTRL_MACTYPE_MASK = 0x7, + MV_V2_PORT_CTRL_MACTYPE_RXAUI = 0x0, + MV_V2_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH = 0x1, + MV_V2_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH = 0x2, + MV_V2_PORT_CTRL_MACTYPE_XAUI = 0x3, + MV_V2_PORT_CTRL_MACTYPE_10GBASER = 0x4, + MV_V2_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN = 0x5, + MV_V2_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6, + MV_V2_PORT_CTRL_MACTYPE_USXGMII = 0x7, /* Temperature control/read registers (88X3310 only) */ MV_V2_TEMP_CTRL = 0xf08a, MV_V2_TEMP_CTRL_MASK = 0xc000, @@ -480,7 +487,7 @@ static int mv3310_config_init(struct phy_device *phydev) if (val < 0) return val; priv->rate_match = ((val & MV_V2_PORT_CTRL_MACTYPE_MASK) == - MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH); + MV_V2_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH); /* Enable EDPD mode - saving 600mW */ return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
Add all MACTYPE definitions for 88X3310/88X3310P. In order to have consistent naming, rename MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH to MV_V2_PORT_CTRL_MACTYPE_10GR_RATE_MATCH. Signed-off-by: Marek Behún <kabel@kernel.org> --- drivers/net/phy/marvell10g.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-)