| Message ID | 20210326031227.2357-2-seiya.wang@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | viresh kumar |
| Headers | show |
| Series | [1/2] clk: mediatek: remove deprecated CLK_INFRA_CA57SEL for MT8173 SoC | expand |
On 26-03-21, 11:12, Seiya Wang wrote: > Update the cpu type of cpu2 and cpu3 since MT8173 used Cortex-a72. > > Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> > --- > Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt > index ea4994b35207..ef68711716fb 100644 > --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt > @@ -202,11 +202,11 @@ Example 2 (MT8173 SoC): > > cpu2: cpu@100 { > device_type = "cpu"; > - compatible = "arm,cortex-a57"; > + compatible = "arm,cortex-a72"; > reg = <0x100>; > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > - clocks = <&infracfg CLK_INFRA_CA57SEL>, > + clocks = <&infracfg CLK_INFRA_CA72SEL>, > <&apmixedsys CLK_APMIXED_MAINPLL>; > clock-names = "cpu", "intermediate"; > operating-points-v2 = <&cpu_opp_table_b>; > @@ -214,11 +214,11 @@ Example 2 (MT8173 SoC): > > cpu3: cpu@101 { > device_type = "cpu"; > - compatible = "arm,cortex-a57"; > + compatible = "arm,cortex-a72"; > reg = <0x101>; > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > - clocks = <&infracfg CLK_INFRA_CA57SEL>, > + clocks = <&infracfg CLK_INFRA_CA72SEL>, > <&apmixedsys CLK_APMIXED_MAINPLL>; > clock-names = "cpu", "intermediate"; > operating-points-v2 = <&cpu_opp_table_b>; Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
On Fri, 26 Mar 2021 11:12:27 +0800, Seiya Wang wrote: > Update the cpu type of cpu2 and cpu3 since MT8173 used Cortex-a72. > > Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> > --- > Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > Acked-by: Rob Herring <robh@kernel.org>
On 26/03/2021 04:12, Seiya Wang wrote: > Update the cpu type of cpu2 and cpu3 since MT8173 used Cortex-a72. > > Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt > index ea4994b35207..ef68711716fb 100644 > --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt > @@ -202,11 +202,11 @@ Example 2 (MT8173 SoC): > > cpu2: cpu@100 { > device_type = "cpu"; > - compatible = "arm,cortex-a57"; > + compatible = "arm,cortex-a72"; > reg = <0x100>; > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > - clocks = <&infracfg CLK_INFRA_CA57SEL>, > + clocks = <&infracfg CLK_INFRA_CA72SEL>, > <&apmixedsys CLK_APMIXED_MAINPLL>; > clock-names = "cpu", "intermediate"; > operating-points-v2 = <&cpu_opp_table_b>; > @@ -214,11 +214,11 @@ Example 2 (MT8173 SoC): > > cpu3: cpu@101 { > device_type = "cpu"; > - compatible = "arm,cortex-a57"; > + compatible = "arm,cortex-a72"; > reg = <0x101>; > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > - clocks = <&infracfg CLK_INFRA_CA57SEL>, > + clocks = <&infracfg CLK_INFRA_CA72SEL>, > <&apmixedsys CLK_APMIXED_MAINPLL>; > clock-names = "cpu", "intermediate"; > operating-points-v2 = <&cpu_opp_table_b>; >
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt index ea4994b35207..ef68711716fb 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt @@ -202,11 +202,11 @@ Example 2 (MT8173 SoC): cpu2: cpu@100 { device_type = "cpu"; - compatible = "arm,cortex-a57"; + compatible = "arm,cortex-a72"; reg = <0x100>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA57SEL>, + clocks = <&infracfg CLK_INFRA_CA72SEL>, <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cpu_opp_table_b>; @@ -214,11 +214,11 @@ Example 2 (MT8173 SoC): cpu3: cpu@101 { device_type = "cpu"; - compatible = "arm,cortex-a57"; + compatible = "arm,cortex-a72"; reg = <0x101>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&infracfg CLK_INFRA_CA57SEL>, + clocks = <&infracfg CLK_INFRA_CA72SEL>, <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cpu_opp_table_b>;
Update the cpu type of cpu2 and cpu3 since MT8173 used Cortex-a72. Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> --- Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)