diff mbox series

[V2] clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback

Message ID 20210406154015.602779-1-quanyang.wang@windriver.com (mailing list archive)
State Accepted, archived
Headers show
Series [V2] clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback | expand

Commit Message

Quanyang Wang April 6, 2021, 3:40 p.m. UTC 
From: Quanyang Wang <quanyang.wang@windriver.com>

The round_rate callback should only perform rate calculation and not
involve calling zynqmp_pll_set_mode to change the pll mode. So let's
move zynqmp_pll_set_mode out of round_rate and to set_rate callback.

Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver")
Reported-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
---
V2:
 - add Fixes tag.
---
 drivers/clk/zynqmp/pll.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Comments

Stephen Boyd April 8, 2021, 1:09 a.m. UTC | #1 
Quoting quanyang.wang@windriver.com (2021-04-06 08:40:15)
> From: Quanyang Wang <quanyang.wang@windriver.com>
> 
> The round_rate callback should only perform rate calculation and not
> involve calling zynqmp_pll_set_mode to change the pll mode. So let's
> move zynqmp_pll_set_mode out of round_rate and to set_rate callback.
> 
> Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver")
> Reported-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
> ---

Applied to clk-next
diff mbox series

Patch

diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c
index 0d64268a4a84..abe6afbf3407 100644
--- a/drivers/clk/zynqmp/pll.c
+++ b/drivers/clk/zynqmp/pll.c
@@ -104,9 +104,7 @@  static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 	/* Enable the fractional mode if needed */
 	rate_div = (rate * FRAC_DIV) / *prate;
 	f = rate_div % FRAC_DIV;
-	zynqmp_pll_set_mode(hw, !!f);
-
-	if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
+	if (f) {
 		if (rate > PS_PLL_VCO_MAX) {
 			fbdiv = rate / PS_PLL_VCO_MAX;
 			rate = rate / (fbdiv + 1);
@@ -177,10 +175,12 @@  static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 	long rate_div, frac, m, f;
 	int ret;
 
-	if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
-		rate_div = (rate * FRAC_DIV) / parent_rate;
+	rate_div = (rate * FRAC_DIV) / parent_rate;
+	f = rate_div % FRAC_DIV;
+	zynqmp_pll_set_mode(hw, !!f);
+
+	if (f) {
 		m = rate_div / FRAC_DIV;
-		f = rate_div % FRAC_DIV;
 		m = clamp_t(u32, m, (PLL_FBDIV_MIN), (PLL_FBDIV_MAX));
 		rate = parent_rate * m;
 		frac = (parent_rate * f) / FRAC_DIV;