diff mbox series

[07/12] usb: dwc2: Update enter clock gating when port is suspended

Message ID 9ed1da9780cddf995841cc5867f195024f5a16d9.1618297800.git.Arthur.Petrosyan@synopsys.com (mailing list archive)
State Accepted
Commit d37b939cf41f6a211d6c5611915c5dd4552cd935
Headers show
Series [01/12] usb: dwc2: Add device clock gating support functions | expand

Commit Message

Artur Petrosyan April 13, 2021, 7:17 a.m. UTC
Updates the implementation of entering clock gating mode
when core receives port suspend.
Instead of setting the required bit fields of the registers
inline, called the "dwc2_host_enter_clock_gating()" function.

Signed-off-by: Artur Petrosyan <Arthur.Petrosyan@synopsys.com>
---
 drivers/usb/dwc2/hcd.c | 19 ++++---------------
 1 file changed, 4 insertions(+), 15 deletions(-)

Comments

Sergey Shtylyov April 13, 2021, 9:22 a.m. UTC | #1
Hello!

On 13.04.2021 10:17, Artur Petrosyan wrote:

> Updates the implementation of entering clock gating mode
> when core receives port suspend.
> Instead of setting the required bit fields of the registers
> inline, called the "dwc2_host_enter_clock_gating()" function.
> 
> Signed-off-by: Artur Petrosyan <Arthur.Petrosyan@synopsys.com>
> ---
>   drivers/usb/dwc2/hcd.c | 19 ++++---------------
>   1 file changed, 4 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
> index 27f030d5de54..e1225fe6c61a 100644
> --- a/drivers/usb/dwc2/hcd.c
> +++ b/drivers/usb/dwc2/hcd.c
[...]
> @@ -3323,22 +3322,12 @@ int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
>   		break;
>   	case DWC2_POWER_DOWN_PARAM_HIBERNATION:
>   	case DWC2_POWER_DOWN_PARAM_NONE:
> -	default:
> -		hprt0 = dwc2_read_hprt0(hsotg);
> -		hprt0 |= HPRT0_SUSP;
> -		dwc2_writel(hsotg, hprt0, HPRT0);
> -		hsotg->bus_suspended = true;
>   		/*
> -		 * If power_down is supported, Phy clock will be suspended
> -		 * after registers are backuped.
> +		 * If not hibernation nor partial power down are supported,

    s/not/neither/?

MBR, Sergei
Greg KH April 13, 2021, 10:24 a.m. UTC | #2
On Tue, Apr 13, 2021 at 12:22:35PM +0300, Sergei Shtylyov wrote:
> Hello!
> 
> On 13.04.2021 10:17, Artur Petrosyan wrote:
> 
> > Updates the implementation of entering clock gating mode
> > when core receives port suspend.
> > Instead of setting the required bit fields of the registers
> > inline, called the "dwc2_host_enter_clock_gating()" function.
> > 
> > Signed-off-by: Artur Petrosyan <Arthur.Petrosyan@synopsys.com>
> > ---
> >   drivers/usb/dwc2/hcd.c | 19 ++++---------------
> >   1 file changed, 4 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
> > index 27f030d5de54..e1225fe6c61a 100644
> > --- a/drivers/usb/dwc2/hcd.c
> > +++ b/drivers/usb/dwc2/hcd.c
> [...]
> > @@ -3323,22 +3322,12 @@ int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
> >   		break;
> >   	case DWC2_POWER_DOWN_PARAM_HIBERNATION:
> >   	case DWC2_POWER_DOWN_PARAM_NONE:
> > -	default:
> > -		hprt0 = dwc2_read_hprt0(hsotg);
> > -		hprt0 |= HPRT0_SUSP;
> > -		dwc2_writel(hsotg, hprt0, HPRT0);
> > -		hsotg->bus_suspended = true;
> >   		/*
> > -		 * If power_down is supported, Phy clock will be suspended
> > -		 * after registers are backuped.
> > +		 * If not hibernation nor partial power down are supported,
> 
>    s/not/neither/?

It's fine, not a big deal at all.

greg k-h
diff mbox series

Patch

diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index 27f030d5de54..e1225fe6c61a 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -3298,7 +3298,6 @@  static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
 int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
 {
 	unsigned long flags;
-	u32 hprt0;
 	u32 pcgctl;
 	u32 gotgctl;
 	int ret = 0;
@@ -3323,22 +3322,12 @@  int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
 		break;
 	case DWC2_POWER_DOWN_PARAM_HIBERNATION:
 	case DWC2_POWER_DOWN_PARAM_NONE:
-	default:
-		hprt0 = dwc2_read_hprt0(hsotg);
-		hprt0 |= HPRT0_SUSP;
-		dwc2_writel(hsotg, hprt0, HPRT0);
-		hsotg->bus_suspended = true;
 		/*
-		 * If power_down is supported, Phy clock will be suspended
-		 * after registers are backuped.
+		 * If not hibernation nor partial power down are supported,
+		 * clock gating is used to save power.
 		 */
-		if (!hsotg->params.power_down) {
-			/* Suspend the Phy Clock */
-			pcgctl = dwc2_readl(hsotg, PCGCTL);
-			pcgctl |= PCGCTL_STOPPCLK;
-			dwc2_writel(hsotg, pcgctl, PCGCTL);
-			udelay(10);
-		}
+		dwc2_host_enter_clock_gating(hsotg);
+		break;
 	}
 
 	/* For HNP the bus must be suspended for at least 200ms */