| Message ID | 1618375222-9283-2-git-send-email-igor.druzhinin@citrix.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v4,1/2] x86/vtx: add LBR_SELECT to the list of LBR MSRs | expand |
On 14.04.2021 06:40, Igor Druzhinin wrote: > LBR, C-state MSRs should correspond to Ice Lake desktop according to > SDM rev. 74 for both models. > > Ice Lake-SP is known to expose IF_PSCHANGE_MC_NO in IA32_ARCH_CAPABILITIES MSR > (as advisory tells and Whitley SDP confirms) which means the erratum is fixed > in hardware for that model and therefore it shouldn't be present in > has_if_pschange_mc list. Provisionally assume the same to be the case > for Ice Lake-D while advisory is not yet updated. > > Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com>
diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index c092086..d788c8b 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -181,6 +181,8 @@ static void do_get_hw_residencies(void *arg) case 0x55: case 0x5E: /* Ice Lake */ + case 0x6A: + case 0x6C: case 0x7D: case 0x7E: /* Tiger Lake */ diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 5a4ca35..52469ca 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2982,7 +2982,7 @@ static const struct lbr_info *last_branch_msr_get(void) /* Goldmont Plus */ case 0x7a: /* Ice Lake */ - case 0x7d: case 0x7e: + case 0x6a: case 0x6c: case 0x7d: case 0x7e: /* Tiger Lake */ case 0x8c: case 0x8d: /* Tremont */
LBR, C-state MSRs should correspond to Ice Lake desktop according to SDM rev. 74 for both models. Ice Lake-SP is known to expose IF_PSCHANGE_MC_NO in IA32_ARCH_CAPABILITIES MSR (as advisory tells and Whitley SDP confirms) which means the erratum is fixed in hardware for that model and therefore it shouldn't be present in has_if_pschange_mc list. Provisionally assume the same to be the case for Ice Lake-D while advisory is not yet updated. Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com> --- Changes in v4: - now based on SDM update - new LBR (0x1e0)does not seem to be exposed in the docs Changes in v3: - Add Ice Lake-D model numbers - Drop has_if_pschange_mc hunk following Tiger Lake related discussion --- xen/arch/x86/acpi/cpu_idle.c | 2 ++ xen/arch/x86/hvm/vmx/vmx.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-)