| Message ID | 20210429084541.28083-1-alex@ghiti.fr (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: Disallow to build XIP_KERNEL with SOC_SIFIVE | expand |
On Thu, Apr 29, 2021 at 2:15 PM Alexandre Ghiti <alex@ghiti.fr> wrote: > > RISCV_ERRATA_ALTERNATIVE patches text at runtime which is not possible when > the kernel is executed from the flash in XIP mode, and as the SIFIVE > errata must be fixed somehow, disallow to build a XIP kernel that > supports SIFIVE socs. > > Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> > --- > arch/riscv/Kconfig.erratas | 2 +- > arch/riscv/Kconfig.socs | 1 + > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas > index d5d03ae8d685..9537dbd67357 100644 > --- a/arch/riscv/Kconfig.erratas > +++ b/arch/riscv/Kconfig.erratas > @@ -2,7 +2,7 @@ menu "CPU errata selection" > > config RISCV_ERRATA_ALTERNATIVE > bool "RISC-V alternative scheme" > - default y > + default y if !XIP_KERNEL > help > This Kconfig allows the kernel to automatically patch the > errata required by the execution platform at run time. The > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > index 00c2b205654c..9cb38bc9d7cd 100644 > --- a/arch/riscv/Kconfig.socs > +++ b/arch/riscv/Kconfig.socs > @@ -9,6 +9,7 @@ config SOC_MICROCHIP_POLARFIRE > > config SOC_SIFIVE > bool "SiFive SoCs" > + depends on !XIP_KERNEL Does this mean that now all SOCs will have to explicitly say "depends on !XIP_KERNEL" How about adding "depends on !XIP_KERNEL" for RISCV_ERRATA_ALTERNATIVE ? Regards, Anup > select SERIAL_SIFIVE if TTY > select SERIAL_SIFIVE_CONSOLE if TTY > select CLK_SIFIVE > -- > 2.20.1 >
On Thu, Apr 29, 2021 at 10:47 AM Alexandre Ghiti <alex@ghiti.fr> wrote: > > RISCV_ERRATA_ALTERNATIVE patches text at runtime which is not possible when > the kernel is executed from the flash in XIP mode, and as the SIFIVE > errata must be fixed somehow, disallow to build a XIP kernel that > supports SIFIVE socs. Could you please hold off this patch for a bit? I will try to come up with an alternative solution. It should be possible to define a special section within the RW area and place the functions that need such patching there. Not that I like that much but at least we'll keep the ability to use XIP on SiFive. Best regards, Vitaly > Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> > --- > arch/riscv/Kconfig.erratas | 2 +- > arch/riscv/Kconfig.socs | 1 + > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas > index d5d03ae8d685..9537dbd67357 100644 > --- a/arch/riscv/Kconfig.erratas > +++ b/arch/riscv/Kconfig.erratas > @@ -2,7 +2,7 @@ menu "CPU errata selection" > > config RISCV_ERRATA_ALTERNATIVE > bool "RISC-V alternative scheme" > - default y > + default y if !XIP_KERNEL > help > This Kconfig allows the kernel to automatically patch the > errata required by the execution platform at run time. The > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > index 00c2b205654c..9cb38bc9d7cd 100644 > --- a/arch/riscv/Kconfig.socs > +++ b/arch/riscv/Kconfig.socs > @@ -9,6 +9,7 @@ config SOC_MICROCHIP_POLARFIRE > > config SOC_SIFIVE > bool "SiFive SoCs" > + depends on !XIP_KERNEL > select SERIAL_SIFIVE if TTY > select SERIAL_SIFIVE_CONSOLE if TTY > select CLK_SIFIVE > -- > 2.20.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
Le 4/29/21 à 5:11 AM, Vitaly Wool a écrit : > On Thu, Apr 29, 2021 at 10:47 AM Alexandre Ghiti <alex@ghiti.fr> wrote: >> >> RISCV_ERRATA_ALTERNATIVE patches text at runtime which is not possible when >> the kernel is executed from the flash in XIP mode, and as the SIFIVE >> errata must be fixed somehow, disallow to build a XIP kernel that >> supports SIFIVE socs. > > Could you please hold off this patch for a bit? I will try to come up > with an alternative solution. It should be possible to define a > special section within the RW area and place the functions that need > such patching there. > Not that I like that much but at least we'll keep the ability to use > XIP on SiFive. Ok, I'm wondering why I did not think of that...I'll give it a try just to punish myself. Thanks Vitaly, Alex > > Best regards, > Vitaly > >> Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> >> --- >> arch/riscv/Kconfig.erratas | 2 +- >> arch/riscv/Kconfig.socs | 1 + >> 2 files changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas >> index d5d03ae8d685..9537dbd67357 100644 >> --- a/arch/riscv/Kconfig.erratas >> +++ b/arch/riscv/Kconfig.erratas >> @@ -2,7 +2,7 @@ menu "CPU errata selection" >> >> config RISCV_ERRATA_ALTERNATIVE >> bool "RISC-V alternative scheme" >> - default y >> + default y if !XIP_KERNEL >> help >> This Kconfig allows the kernel to automatically patch the >> errata required by the execution platform at run time. The >> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs >> index 00c2b205654c..9cb38bc9d7cd 100644 >> --- a/arch/riscv/Kconfig.socs >> +++ b/arch/riscv/Kconfig.socs >> @@ -9,6 +9,7 @@ config SOC_MICROCHIP_POLARFIRE >> >> config SOC_SIFIVE >> bool "SiFive SoCs" >> + depends on !XIP_KERNEL >> select SERIAL_SIFIVE if TTY >> select SERIAL_SIFIVE_CONSOLE if TTY >> select CLK_SIFIVE >> -- >> 2.20.1 >> >> >> _______________________________________________ >> linux-riscv mailing list >> linux-riscv@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-riscv > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv >
Le 4/29/21 à 5:04 AM, Anup Patel a écrit : > On Thu, Apr 29, 2021 at 2:15 PM Alexandre Ghiti <alex@ghiti.fr> wrote: >> >> RISCV_ERRATA_ALTERNATIVE patches text at runtime which is not possible when >> the kernel is executed from the flash in XIP mode, and as the SIFIVE >> errata must be fixed somehow, disallow to build a XIP kernel that >> supports SIFIVE socs. >> >> Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> >> --- >> arch/riscv/Kconfig.erratas | 2 +- >> arch/riscv/Kconfig.socs | 1 + >> 2 files changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas >> index d5d03ae8d685..9537dbd67357 100644 >> --- a/arch/riscv/Kconfig.erratas >> +++ b/arch/riscv/Kconfig.erratas >> @@ -2,7 +2,7 @@ menu "CPU errata selection" >> >> config RISCV_ERRATA_ALTERNATIVE >> bool "RISC-V alternative scheme" >> - default y >> + default y if !XIP_KERNEL >> help >> This Kconfig allows the kernel to automatically patch the >> errata required by the execution platform at run time. The >> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs >> index 00c2b205654c..9cb38bc9d7cd 100644 >> --- a/arch/riscv/Kconfig.socs >> +++ b/arch/riscv/Kconfig.socs >> @@ -9,6 +9,7 @@ config SOC_MICROCHIP_POLARFIRE >> >> config SOC_SIFIVE >> bool "SiFive SoCs" >> + depends on !XIP_KERNEL > > Does this mean that now all SOCs will have to explicitly say > "depends on !XIP_KERNEL" > > How about adding "depends on !XIP_KERNEL" for RISCV_ERRATA_ALTERNATIVE ? In any case, I had to add this because I could not get rid of the following warnings: WARNING: unmet direct dependencies detected for ERRATA_SIFIVE Depends on [n]: RISCV_ERRATA_ALTERNATIVE [=n] Selected by [y]: - SOC_SIFIVE [=y] If you have a solution for that, without touching any SOC_* config, I'll take it. I'll try to implement what Vitaly proposed as it sounds way better than this "bandage" patch. Thanks Anup, Alex > > Regards, > Anup > >> select SERIAL_SIFIVE if TTY >> select SERIAL_SIFIVE_CONSOLE if TTY >> select CLK_SIFIVE >> -- >> 2.20.1 >> > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv >
Le 4/29/21 à 8:13 AM, Alex Ghiti a écrit : > Le 4/29/21 à 5:11 AM, Vitaly Wool a écrit : >> On Thu, Apr 29, 2021 at 10:47 AM Alexandre Ghiti <alex@ghiti.fr> wrote: >>> >>> RISCV_ERRATA_ALTERNATIVE patches text at runtime which is not >>> possible when >>> the kernel is executed from the flash in XIP mode, and as the SIFIVE >>> errata must be fixed somehow, disallow to build a XIP kernel that >>> supports SIFIVE socs. >> >> Could you please hold off this patch for a bit? I will try to come up >> with an alternative solution. It should be possible to define a >> special section within the RW area and place the functions that need >> such patching there. >> Not that I like that much but at least we'll keep the ability to use >> XIP on SiFive. > > Ok, I'm wondering why I did not think of that...I'll give it a try just > to punish myself. > > Thanks Vitaly, > > Alex > I tried what you proposed and it works well, *callers* must be placed into this writable section in RAM and that's it, that may be more complicated if at some point the patched functions are generic but I think we can use an intermediate riscv function to patch instead or something else. The modifications I did only consist in putting alternative section in RAM and place the exception vector table in this section. If you can do the proper patch, I'll let you do it, otherwise I'll do that later as I have other things to do before. So Palmer you can drop this patch. Thanks again, >> >> Best regards, >> Vitaly >> >>> Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> >>> --- >>> arch/riscv/Kconfig.erratas | 2 +- >>> arch/riscv/Kconfig.socs | 1 + >>> 2 files changed, 2 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas >>> index d5d03ae8d685..9537dbd67357 100644 >>> --- a/arch/riscv/Kconfig.erratas >>> +++ b/arch/riscv/Kconfig.erratas >>> @@ -2,7 +2,7 @@ menu "CPU errata selection" >>> >>> config RISCV_ERRATA_ALTERNATIVE >>> bool "RISC-V alternative scheme" >>> - default y >>> + default y if !XIP_KERNEL >>> help >>> This Kconfig allows the kernel to automatically patch the >>> errata required by the execution platform at run time. The >>> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs >>> index 00c2b205654c..9cb38bc9d7cd 100644 >>> --- a/arch/riscv/Kconfig.socs >>> +++ b/arch/riscv/Kconfig.socs >>> @@ -9,6 +9,7 @@ config SOC_MICROCHIP_POLARFIRE >>> >>> config SOC_SIFIVE >>> bool "SiFive SoCs" >>> + depends on !XIP_KERNEL >>> select SERIAL_SIFIVE if TTY >>> select SERIAL_SIFIVE_CONSOLE if TTY >>> select CLK_SIFIVE >>> -- >>> 2.20.1 >>> >>> >>> _______________________________________________ >>> linux-riscv mailing list >>> linux-riscv@lists.infradead.org >>> http://lists.infradead.org/mailman/listinfo/linux-riscv >> >> _______________________________________________ >> linux-riscv mailing list >> linux-riscv@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-riscv >> > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Fri, 30 Apr 2021 01:09:14 PDT (-0700), alex@ghiti.fr wrote: > Le 4/29/21 à 8:13 AM, Alex Ghiti a écrit : >> Le 4/29/21 à 5:11 AM, Vitaly Wool a écrit : >>> On Thu, Apr 29, 2021 at 10:47 AM Alexandre Ghiti <alex@ghiti.fr> wrote: >>>> >>>> RISCV_ERRATA_ALTERNATIVE patches text at runtime which is not >>>> possible when >>>> the kernel is executed from the flash in XIP mode, and as the SIFIVE >>>> errata must be fixed somehow, disallow to build a XIP kernel that >>>> supports SIFIVE socs. >>> >>> Could you please hold off this patch for a bit? I will try to come up >>> with an alternative solution. It should be possible to define a >>> special section within the RW area and place the functions that need >>> such patching there. >>> Not that I like that much but at least we'll keep the ability to use >>> XIP on SiFive. >> >> Ok, I'm wondering why I did not think of that...I'll give it a try just >> to punish myself. >> >> Thanks Vitaly, >> >> Alex >> > > I tried what you proposed and it works well, *callers* must be placed > into this writable section in RAM and that's it, that may be more > complicated if at some point the patched functions are generic but I > think we can use an intermediate riscv function to patch instead or > something else. > > The modifications I did only consist in putting alternative section in > RAM and place the exception vector table in this section. > > If you can do the proper patch, I'll let you do it, otherwise I'll do > that later as I have other things to do before. > > So Palmer you can drop this patch. Great. I was going to push back and just say "we should swap the alternatives over to the errata implemnetation for XIP, as the current ones are just a performance hit when unnecessary and XIP users are likely to build for a single SOC anyway". That would mean we'd need to sort something out WRT errata that rely on design-specific functionality, and everything I came up with there was a headache. It's way better if we can just full support the alternatives stuff, so I'll just wait for that. > > Thanks again, > >>> >>> Best regards, >>> Vitaly >>> >>>> Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> >>>> --- >>>> arch/riscv/Kconfig.erratas | 2 +- >>>> arch/riscv/Kconfig.socs | 1 + >>>> 2 files changed, 2 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas >>>> index d5d03ae8d685..9537dbd67357 100644 >>>> --- a/arch/riscv/Kconfig.erratas >>>> +++ b/arch/riscv/Kconfig.erratas >>>> @@ -2,7 +2,7 @@ menu "CPU errata selection" >>>> >>>> config RISCV_ERRATA_ALTERNATIVE >>>> bool "RISC-V alternative scheme" >>>> - default y >>>> + default y if !XIP_KERNEL >>>> help >>>> This Kconfig allows the kernel to automatically patch the >>>> errata required by the execution platform at run time. The >>>> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs >>>> index 00c2b205654c..9cb38bc9d7cd 100644 >>>> --- a/arch/riscv/Kconfig.socs >>>> +++ b/arch/riscv/Kconfig.socs >>>> @@ -9,6 +9,7 @@ config SOC_MICROCHIP_POLARFIRE >>>> >>>> config SOC_SIFIVE >>>> bool "SiFive SoCs" >>>> + depends on !XIP_KERNEL >>>> select SERIAL_SIFIVE if TTY >>>> select SERIAL_SIFIVE_CONSOLE if TTY >>>> select CLK_SIFIVE >>>> -- >>>> 2.20.1 >>>> >>>> >>>> _______________________________________________ >>>> linux-riscv mailing list >>>> linux-riscv@lists.infradead.org >>>> http://lists.infradead.org/mailman/listinfo/linux-riscv >>> >>> _______________________________________________ >>> linux-riscv mailing list >>> linux-riscv@lists.infradead.org >>> http://lists.infradead.org/mailman/listinfo/linux-riscv >>> >> >> _______________________________________________ >> linux-riscv mailing list >> linux-riscv@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas index d5d03ae8d685..9537dbd67357 100644 --- a/arch/riscv/Kconfig.erratas +++ b/arch/riscv/Kconfig.erratas @@ -2,7 +2,7 @@ menu "CPU errata selection" config RISCV_ERRATA_ALTERNATIVE bool "RISC-V alternative scheme" - default y + default y if !XIP_KERNEL help This Kconfig allows the kernel to automatically patch the errata required by the execution platform at run time. The diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 00c2b205654c..9cb38bc9d7cd 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -9,6 +9,7 @@ config SOC_MICROCHIP_POLARFIRE config SOC_SIFIVE bool "SiFive SoCs" + depends on !XIP_KERNEL select SERIAL_SIFIVE if TTY select SERIAL_SIFIVE_CONSOLE if TTY select CLK_SIFIVE
RISCV_ERRATA_ALTERNATIVE patches text at runtime which is not possible when the kernel is executed from the flash in XIP mode, and as the SIFIVE errata must be fixed somehow, disallow to build a XIP kernel that supports SIFIVE socs. Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> --- arch/riscv/Kconfig.erratas | 2 +- arch/riscv/Kconfig.socs | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)