| Message ID | 20210504184925.3399934-1-sean.anderson@seco.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/2] dt-bindings: pwm: Add Xilinx AXI Timer | expand |
On 5/4/21 8:49 PM, Sean Anderson wrote: > This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is > a "soft" block, so it has many parameters which would not be > configurable in most hardware. This binding is usually automatically > generated by Xilinx's tools, so the names and values of properties > must be kept as they are. > > Signed-off-by: Sean Anderson <sean.anderson@seco.com> > --- > > Changes in v2: > - Use 32-bit addresses for example binding > > .../bindings/pwm/xlnx,axi-timer.yaml | 91 +++++++++++++++++++ > 1 file changed, 91 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > new file mode 100644 > index 000000000000..bd014134c322 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > @@ -0,0 +1,91 @@ > +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/xlnx,axi-timer.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding > + > +maintainers: > + - Sean Anderson <sean.anderson@seco.com> > + > +properties: > + compatible: > + items: > + - const: xlnx,axi-timer-2.0 > + - const: xlnx,xps-timer-1.00.a > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: s_axi_aclk > + > + reg: > + maxItems: 1 > + > + xlnx,count-width: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 8 > + maximum: 32 > + description: > + The width of the counters, in bits. > + > + xlnx,gen0-assert: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + The polarity of the generateout0 signal. 0 for active-low, 1 for active-high. > + > + xlnx,gen1-assert: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + The polarity of the generateout1 signal. 0 for active-low, 1 for active-high. > + > + xlnx,one-timer-only: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + Whether only one timer is present in this block. > + > + xlnx,trig0-assert: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + The polarity of the capturetrig0 signal. 0 for active-low, 1 for active-high. > + > + xlnx,trig1-assert: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + The polarity of the capturetrig1 signal. 0 for active-low, 1 for active-high. > + Based on xilinx design tool selection there is also mode_64bit option which I expect will be translate to xlnx,mode-64bit [0, 1]. But any coverage of this as bool property should be fine. > +required: > + - compatible > + - clocks > + - reg > + - xlnx,count-width > + - xlnx,gen0-assert > + - xlnx,gen1-assert these 3 shouldn't be required. > + - xlnx,one-timer-only > + - xlnx,trig0-assert > + - xlnx,trig1-assert these 2 are also not required. > + > +additionalProperties: true > + > +examples: > + - | > + axi_timer_0: timer@800e0000 { > + clock-frequency = <99999001>; I can't see this listed above. It is allowed to have additional properties but I don't think it is good to list it here. > + clock-names = "s_axi_aclk"; > + clocks = <&zynqmp_clk 71>; > + compatible = "xlnx,axi-timer-2.0", "xlnx,xps-timer-1.00.a"; > + reg = <0x800e0000 0x10000>; > + xlnx,count-width = <0x20>; > + xlnx,gen0-assert = <0x1>; > + xlnx,gen1-assert = <0x1>; > + xlnx,one-timer-only = <0x0>; > + xlnx,trig0-assert = <0x1>; > + xlnx,trig1-assert = <0x1>; > + }; > Thanks, Michal
On 5/5/21 2:46 AM, Michal Simek wrote: > > > On 5/4/21 8:49 PM, Sean Anderson wrote: >> This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is >> a "soft" block, so it has many parameters which would not be >> configurable in most hardware. This binding is usually automatically >> generated by Xilinx's tools, so the names and values of properties >> must be kept as they are. >> >> Signed-off-by: Sean Anderson <sean.anderson@seco.com> >> --- >> >> Changes in v2: >> - Use 32-bit addresses for example binding >> >> .../bindings/pwm/xlnx,axi-timer.yaml | 91 +++++++++++++++++++ >> 1 file changed, 91 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >> >> diff --git a/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >> new file mode 100644 >> index 000000000000..bd014134c322 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >> @@ -0,0 +1,91 @@ >> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pwm/xlnx,axi-timer.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding >> + >> +maintainers: >> + - Sean Anderson <sean.anderson@seco.com> >> + >> +properties: >> + compatible: >> + items: >> + - const: xlnx,axi-timer-2.0 >> + - const: xlnx,xps-timer-1.00.a >> + >> + clocks: >> + maxItems: 1 >> + >> + clock-names: >> + const: s_axi_aclk >> + >> + reg: >> + maxItems: 1 >> + >> + xlnx,count-width: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + minimum: 8 >> + maximum: 32 >> + description: >> + The width of the counters, in bits. >> + >> + xlnx,gen0-assert: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [ 0, 1 ] >> + description: >> + The polarity of the generateout0 signal. 0 for active-low, 1 for active-high. >> + >> + xlnx,gen1-assert: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [ 0, 1 ] >> + description: >> + The polarity of the generateout1 signal. 0 for active-low, 1 for active-high. >> + >> + xlnx,one-timer-only: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [ 0, 1 ] >> + description: >> + Whether only one timer is present in this block. >> + >> + xlnx,trig0-assert: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [ 0, 1 ] >> + description: >> + The polarity of the capturetrig0 signal. 0 for active-low, 1 for active-high. >> + >> + xlnx,trig1-assert: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [ 0, 1 ] >> + description: >> + The polarity of the capturetrig1 signal. 0 for active-low, 1 for active-high. >> + > > Based on xilinx design tool selection there is also mode_64bit option > which I expect will be translate to xlnx,mode-64bit [0, 1]. > But any coverage of this as bool property should be fine. I believe that just selects count-width=32 and one-timer-only=0. From the data sheet, there doesn't appear to be a separate mode-64bit parameter. > >> +required: >> + - compatible >> + - clocks >> + - reg >> + - xlnx,count-width >> + - xlnx,gen0-assert >> + - xlnx,gen1-assert > > these 3 shouldn't be required. Count width is certainly required so that we can determine the correct value to program into TLR. For the PWM driver, gen?-assert are required to determine whether PWM mode is enabled. > >> + - xlnx,one-timer-only >> + - xlnx,trig0-assert >> + - xlnx,trig1-assert > > these 2 are also not required. These are not currently required by the driver, but might be in the future if capture mode support is enabled. In general, since these properties cannot be determined from the hardware, I think they should be present in the devicetree. > > >> + >> +additionalProperties: true >> + >> +examples: >> + - | >> + axi_timer_0: timer@800e0000 { >> + clock-frequency = <99999001>; > > I can't see this listed above. It is allowed to have additional > properties but I don't think it is good to list it here. This is just the direct output of Xilinx's generated device tree (but with address width reduced to 32-bit). --Sean > >> + clock-names = "s_axi_aclk"; >> + clocks = <&zynqmp_clk 71>; >> + compatible = "xlnx,axi-timer-2.0", "xlnx,xps-timer-1.00.a"; >> + reg = <0x800e0000 0x10000>; >> + xlnx,count-width = <0x20>; >> + xlnx,gen0-assert = <0x1>; >> + xlnx,gen1-assert = <0x1>; >> + xlnx,one-timer-only = <0x0>; >> + xlnx,trig0-assert = <0x1>; >> + xlnx,trig1-assert = <0x1>; >> + }; >> > > Thanks, > Michal >
On Tue, May 04, 2021 at 02:49:24PM -0400, Sean Anderson wrote: > This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is > a "soft" block, so it has many parameters which would not be > configurable in most hardware. This binding is usually automatically > generated by Xilinx's tools, so the names and values of properties > must be kept as they are. > > Signed-off-by: Sean Anderson <sean.anderson@seco.com> > --- > > Changes in v2: > - Use 32-bit addresses for example binding > > .../bindings/pwm/xlnx,axi-timer.yaml | 91 +++++++++++++++++++ > 1 file changed, 91 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > new file mode 100644 > index 000000000000..bd014134c322 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > @@ -0,0 +1,91 @@ > +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/xlnx,axi-timer.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding > + > +maintainers: > + - Sean Anderson <sean.anderson@seco.com> > + > +properties: > + compatible: > + items: > + - const: xlnx,axi-timer-2.0 > + - const: xlnx,xps-timer-1.00.a > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: s_axi_aclk > + > + reg: > + maxItems: 1 > + > + xlnx,count-width: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 8 > + maximum: 32 > + description: > + The width of the counters, in bits. > + > + xlnx,gen0-assert: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + The polarity of the generateout0 signal. 0 for active-low, 1 for active-high. > + > + xlnx,gen1-assert: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + The polarity of the generateout1 signal. 0 for active-low, 1 for active-high. > + > + xlnx,one-timer-only: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + Whether only one timer is present in this block. > + > + xlnx,trig0-assert: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + The polarity of the capturetrig0 signal. 0 for active-low, 1 for active-high. > + > + xlnx,trig1-assert: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + The polarity of the capturetrig1 signal. 0 for active-low, 1 for active-high. Can't all these be boolean? > + > +required: > + - compatible > + - clocks > + - reg > + - xlnx,count-width > + - xlnx,gen0-assert > + - xlnx,gen1-assert > + - xlnx,one-timer-only > + - xlnx,trig0-assert > + - xlnx,trig1-assert > + > +additionalProperties: true > + > +examples: > + - | > + axi_timer_0: timer@800e0000 { > + clock-frequency = <99999001>; > + clock-names = "s_axi_aclk"; > + clocks = <&zynqmp_clk 71>; > + compatible = "xlnx,axi-timer-2.0", "xlnx,xps-timer-1.00.a"; > + reg = <0x800e0000 0x10000>; > + xlnx,count-width = <0x20>; > + xlnx,gen0-assert = <0x1>; > + xlnx,gen1-assert = <0x1>; > + xlnx,one-timer-only = <0x0>; > + xlnx,trig0-assert = <0x1>; > + xlnx,trig1-assert = <0x1>; > + }; > -- > 2.25.1 >
On 5/6/21 5:05 PM, Rob Herring wrote: > On Tue, May 04, 2021 at 02:49:24PM -0400, Sean Anderson wrote: >> This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is >> a "soft" block, so it has many parameters which would not be >> configurable in most hardware. This binding is usually automatically >> generated by Xilinx's tools, so the names and values of properties >> must be kept as they are. >> >> Signed-off-by: Sean Anderson <sean.anderson@seco.com> >> --- >> >> Changes in v2: >> - Use 32-bit addresses for example binding >> >> .../bindings/pwm/xlnx,axi-timer.yaml | 91 +++++++++++++++++++ >> 1 file changed, 91 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >> >> diff --git a/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >> new file mode 100644 >> index 000000000000..bd014134c322 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >> @@ -0,0 +1,91 @@ >> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pwm/xlnx,axi-timer.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding >> + >> +maintainers: >> + - Sean Anderson <sean.anderson@seco.com> >> + >> +properties: >> + compatible: >> + items: >> + - const: xlnx,axi-timer-2.0 >> + - const: xlnx,xps-timer-1.00.a >> + >> + clocks: >> + maxItems: 1 >> + >> + clock-names: >> + const: s_axi_aclk >> + >> + reg: >> + maxItems: 1 >> + >> + xlnx,count-width: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + minimum: 8 >> + maximum: 32 >> + description: >> + The width of the counters, in bits. >> + >> + xlnx,gen0-assert: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [ 0, 1 ] >> + description: >> + The polarity of the generateout0 signal. 0 for active-low, 1 for active-high. >> + >> + xlnx,gen1-assert: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [ 0, 1 ] >> + description: >> + The polarity of the generateout1 signal. 0 for active-low, 1 for active-high. >> + >> + xlnx,one-timer-only: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [ 0, 1 ] >> + description: >> + Whether only one timer is present in this block. >> + >> + xlnx,trig0-assert: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [ 0, 1 ] >> + description: >> + The polarity of the capturetrig0 signal. 0 for active-low, 1 for active-high. >> + >> + xlnx,trig1-assert: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [ 0, 1 ] >> + description: >> + The polarity of the capturetrig1 signal. 0 for active-low, 1 for active-high. > > Can't all these be boolean? They could, but > This binding is usually automatically generated by Xilinx's tools, so > the names and values of properties must be kept as they are. Because this is a soft device, the binding may be (very conveniently) auto-generated. I am not opposed to adding additional properties which could be used by new code, but we should still accept this auto-generated output. --Sean > >> + >> +required: >> + - compatible >> + - clocks >> + - reg >> + - xlnx,count-width >> + - xlnx,gen0-assert >> + - xlnx,gen1-assert >> + - xlnx,one-timer-only >> + - xlnx,trig0-assert >> + - xlnx,trig1-assert >> + >> +additionalProperties: true >> + >> +examples: >> + - | >> + axi_timer_0: timer@800e0000 { >> + clock-frequency = <99999001>; >> + clock-names = "s_axi_aclk"; >> + clocks = <&zynqmp_clk 71>; >> + compatible = "xlnx,axi-timer-2.0", "xlnx,xps-timer-1.00.a"; >> + reg = <0x800e0000 0x10000>; >> + xlnx,count-width = <0x20>; >> + xlnx,gen0-assert = <0x1>; >> + xlnx,gen1-assert = <0x1>; >> + xlnx,one-timer-only = <0x0>; >> + xlnx,trig0-assert = <0x1>; >> + xlnx,trig1-assert = <0x1>; >> + }; >> -- >> 2.25.1 >>
On 5/6/21 11:10 PM, Sean Anderson wrote: > > > On 5/6/21 5:05 PM, Rob Herring wrote: >> On Tue, May 04, 2021 at 02:49:24PM -0400, Sean Anderson wrote: >>> This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is >>> a "soft" block, so it has many parameters which would not be >>> configurable in most hardware. This binding is usually automatically >>> generated by Xilinx's tools, so the names and values of properties >>> must be kept as they are. >>> >>> Signed-off-by: Sean Anderson <sean.anderson@seco.com> >>> --- >>> >>> Changes in v2: >>> - Use 32-bit addresses for example binding >>> >>> .../bindings/pwm/xlnx,axi-timer.yaml | 91 +++++++++++++++++++ >>> 1 file changed, 91 insertions(+) >>> create mode 100644 > Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >>> >>> diff --git > a/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >>> new file mode 100644 >>> index 000000000000..bd014134c322 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >>> @@ -0,0 +1,91 @@ >>> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/pwm/xlnx,axi-timer.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding >>> + >>> +maintainers: >>> + - Sean Anderson <sean.anderson@seco.com> >>> + >>> +properties: >>> + compatible: >>> + items: >>> + - const: xlnx,axi-timer-2.0 >>> + - const: xlnx,xps-timer-1.00.a >>> + >>> + clocks: >>> + maxItems: 1 >>> + >>> + clock-names: >>> + const: s_axi_aclk >>> + >>> + reg: >>> + maxItems: 1 >>> + >>> + xlnx,count-width: >>> + $ref: /schemas/types.yaml#/definitions/uint32 >>> + minimum: 8 >>> + maximum: 32 >>> + description: >>> + The width of the counters, in bits. >>> + >>> + xlnx,gen0-assert: >>> + $ref: /schemas/types.yaml#/definitions/uint32 >>> + enum: [ 0, 1 ] >>> + description: >>> + The polarity of the generateout0 signal. 0 for active-low, 1 > for active-high. >>> + >>> + xlnx,gen1-assert: >>> + $ref: /schemas/types.yaml#/definitions/uint32 >>> + enum: [ 0, 1 ] >>> + description: >>> + The polarity of the generateout1 signal. 0 for active-low, 1 > for active-high. >>> + >>> + xlnx,one-timer-only: >>> + $ref: /schemas/types.yaml#/definitions/uint32 >>> + enum: [ 0, 1 ] >>> + description: >>> + Whether only one timer is present in this block. >>> + >>> + xlnx,trig0-assert: >>> + $ref: /schemas/types.yaml#/definitions/uint32 >>> + enum: [ 0, 1 ] >>> + description: >>> + The polarity of the capturetrig0 signal. 0 for active-low, 1 > for active-high. >>> + >>> + xlnx,trig1-assert: >>> + $ref: /schemas/types.yaml#/definitions/uint32 >>> + enum: [ 0, 1 ] >>> + description: >>> + The polarity of the capturetrig1 signal. 0 for active-low, 1 > for active-high. >> >> Can't all these be boolean? > > They could, but > >> This binding is usually automatically generated by Xilinx's tools, so >> the names and values of properties must be kept as they are. > > Because this is a soft device, the binding may be (very conveniently) > auto-generated. I am not opposed to adding additional properties which > could be used by new code, but we should still accept this auto-generated > output. I think in this case you should described what it is used by current driver in Microblaze and these options are required. The rest are by design optional. If you want to change them to different value then current binding should be deprecated and have any transition time with code alignment. Thanks, Michal
On 5/7/21 2:35 AM, Michal Simek wrote: > > > On 5/6/21 11:10 PM, Sean Anderson wrote: >> >> >> On 5/6/21 5:05 PM, Rob Herring wrote: >>> On Tue, May 04, 2021 at 02:49:24PM -0400, Sean Anderson wrote: >>>> This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is >>>> a "soft" block, so it has many parameters which would not be >>>> configurable in most hardware. This binding is usually automatically >>>> generated by Xilinx's tools, so the names and values of properties >>>> must be kept as they are. >>>> >>>> Signed-off-by: Sean Anderson <sean.anderson@seco.com> >>>> --- >>>> >>>> Changes in v2: >>>> - Use 32-bit addresses for example binding >>>> >>>> .../bindings/pwm/xlnx,axi-timer.yaml | 91 +++++++++++++++++++ >>>> 1 file changed, 91 insertions(+) >>>> create mode 100644 >> Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >>>> >>>> diff --git >> a/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >> b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >>>> new file mode 100644 >>>> index 000000000000..bd014134c322 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >>>> @@ -0,0 +1,91 @@ >>>> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause >>>> +%YAML 1.2 >>>> +--- >>>> +$id: http://devicetree.org/schemas/pwm/xlnx,axi-timer.yaml# >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding >>>> + >>>> +maintainers: >>>> + - Sean Anderson <sean.anderson@seco.com> >>>> + >>>> +properties: >>>> + compatible: >>>> + items: >>>> + - const: xlnx,axi-timer-2.0 >>>> + - const: xlnx,xps-timer-1.00.a >>>> + >>>> + clocks: >>>> + maxItems: 1 >>>> + >>>> + clock-names: >>>> + const: s_axi_aclk >>>> + >>>> + reg: >>>> + maxItems: 1 >>>> + >>>> + xlnx,count-width: >>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>> + minimum: 8 >>>> + maximum: 32 >>>> + description: >>>> + The width of the counters, in bits. >>>> + >>>> + xlnx,gen0-assert: >>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>> + enum: [ 0, 1 ] >>>> + description: >>>> + The polarity of the generateout0 signal. 0 for active-low, 1 >> for active-high. >>>> + >>>> + xlnx,gen1-assert: >>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>> + enum: [ 0, 1 ] >>>> + description: >>>> + The polarity of the generateout1 signal. 0 for active-low, 1 >> for active-high. >>>> + >>>> + xlnx,one-timer-only: >>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>> + enum: [ 0, 1 ] >>>> + description: >>>> + Whether only one timer is present in this block. >>>> + >>>> + xlnx,trig0-assert: >>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>> + enum: [ 0, 1 ] >>>> + description: >>>> + The polarity of the capturetrig0 signal. 0 for active-low, 1 >> for active-high. >>>> + >>>> + xlnx,trig1-assert: >>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>> + enum: [ 0, 1 ] >>>> + description: >>>> + The polarity of the capturetrig1 signal. 0 for active-low, 1 >> for active-high. >>> >>> Can't all these be boolean? >> >> They could, but >> >>> This binding is usually automatically generated by Xilinx's tools, so >>> the names and values of properties must be kept as they are. >> >> Because this is a soft device, the binding may be (very conveniently) >> auto-generated. I am not opposed to adding additional properties which >> could be used by new code, but we should still accept this auto-generated >> output. > > I think in this case you should described what it is used by current > driver in Microblaze and these options are required. The rest are by > design optional. > If you want to change them to different value then current binding > should be deprecated and have any transition time with code alignment. Well, every single one of these is in the microblaze devicetree since 2009. And fundamentally, all of these are required for a complete driver implementation. They are generally not discoverable from hardware (though I think it might be possible for one-timer-only or perhaps counter-width by inspecting whether register writes stick). However, the signal polarity properties are required to determine whether PWM mode is possible, and to determine the polarity of PWM capture (if that is implemented in the future). I think allowing more conventional usage of devicetree is a good idea. E.g. we could accept both something like 'xlnx,gen0-assert = <0>;' and 'xlnx,gen0-active-low;'. But I think we should still parse older devicetree properties, given the (likely extensive) amount of existing devicetrees with this binding. And this would also require Xilinx to adopt whatever we decide on, and update their devicetree generators accordingly. --Sean
diff --git a/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml new file mode 100644 index 000000000000..bd014134c322 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/xlnx,axi-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding + +maintainers: + - Sean Anderson <sean.anderson@seco.com> + +properties: + compatible: + items: + - const: xlnx,axi-timer-2.0 + - const: xlnx,xps-timer-1.00.a + + clocks: + maxItems: 1 + + clock-names: + const: s_axi_aclk + + reg: + maxItems: 1 + + xlnx,count-width: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 8 + maximum: 32 + description: + The width of the counters, in bits. + + xlnx,gen0-assert: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + description: + The polarity of the generateout0 signal. 0 for active-low, 1 for active-high. + + xlnx,gen1-assert: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + description: + The polarity of the generateout1 signal. 0 for active-low, 1 for active-high. + + xlnx,one-timer-only: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + description: + Whether only one timer is present in this block. + + xlnx,trig0-assert: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + description: + The polarity of the capturetrig0 signal. 0 for active-low, 1 for active-high. + + xlnx,trig1-assert: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + description: + The polarity of the capturetrig1 signal. 0 for active-low, 1 for active-high. + +required: + - compatible + - clocks + - reg + - xlnx,count-width + - xlnx,gen0-assert + - xlnx,gen1-assert + - xlnx,one-timer-only + - xlnx,trig0-assert + - xlnx,trig1-assert + +additionalProperties: true + +examples: + - | + axi_timer_0: timer@800e0000 { + clock-frequency = <99999001>; + clock-names = "s_axi_aclk"; + clocks = <&zynqmp_clk 71>; + compatible = "xlnx,axi-timer-2.0", "xlnx,xps-timer-1.00.a"; + reg = <0x800e0000 0x10000>; + xlnx,count-width = <0x20>; + xlnx,gen0-assert = <0x1>; + xlnx,gen1-assert = <0x1>; + xlnx,one-timer-only = <0x0>; + xlnx,trig0-assert = <0x1>; + xlnx,trig1-assert = <0x1>; + };
This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is a "soft" block, so it has many parameters which would not be configurable in most hardware. This binding is usually automatically generated by Xilinx's tools, so the names and values of properties must be kept as they are. Signed-off-by: Sean Anderson <sean.anderson@seco.com> --- Changes in v2: - Use 32-bit addresses for example binding .../bindings/pwm/xlnx,axi-timer.yaml | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml