| Message ID | 20210504082052.2084706-1-l.stach@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] arm64: dts: imx8mm: specify dma-ranges | expand |
On 04.05.21 10:20, Lucas Stach wrote: > DMA addressing capabilities on i.MX8MM are limited by the interconnect, > same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let > the kernel know about this. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> With this applied the following errors don't occur anymore when using the GPU with a board that has 4GB of RAM. etnaviv-gpu 38000000.gpu: AXI bus error etnaviv-gpu 38000000.gpu: MMU fault status 0x00000000 etnaviv-gpu 38000000.gpu: recover hung GPU! > --- > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > index 6bf1d15ba16a..5bdc730f6132 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -261,6 +261,7 @@ soc@0 { > #address-cells = <1>; > #size-cells = <1>; > ranges = <0x0 0x0 0x0 0x3e000000>; > + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; > nvmem-cells = <&imx8mm_uid>; > nvmem-cell-names = "soc_unique_id"; > >
On Tue, May 4, 2021 at 3:21 AM Lucas Stach <l.stach@pengutronix.de> wrote: > > DMA addressing capabilities on i.MX8MM are limited by the interconnect, > same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let > the kernel know about this. Can you point me to the section of the reference manual where this is found? I'm guessing a similar thing would be applicable to the 8M Nano as well, but I want to understand first. thanks adam > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > index 6bf1d15ba16a..5bdc730f6132 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -261,6 +261,7 @@ soc@0 { > #address-cells = <1>; > #size-cells = <1>; > ranges = <0x0 0x0 0x0 0x3e000000>; > + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; > nvmem-cells = <&imx8mm_uid>; > nvmem-cell-names = "soc_unique_id"; > > -- > 2.29.2 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Am Mittwoch, dem 05.05.2021 um 06:36 -0500 schrieb Adam Ford: > On Tue, May 4, 2021 at 3:21 AM Lucas Stach <l.stach@pengutronix.de> wrote: > > > > DMA addressing capabilities on i.MX8MM are limited by the interconnect, > > same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let > > the kernel know about this. > > Can you point me to the section of the reference manual where this is > found? I'm guessing a similar thing would be applicable to the 8M > Nano as well, but I want to understand first. The second patch in this series already fixes up the 8MN DT. The relevant part of the RM is section 2.1.2 (Cortex-A53 memory map) where you can see that the DDR above the 4GB mark is only accessible to the A53 cluster, other DMA masters only have access to the 3GB located below the 4GB mark. Regards, Lucas > thanks > > adam > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > --- > > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > index 6bf1d15ba16a..5bdc730f6132 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > @@ -261,6 +261,7 @@ soc@0 { > > #address-cells = <1>; > > #size-cells = <1>; > > ranges = <0x0 0x0 0x0 0x3e000000>; > > + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; > > nvmem-cells = <&imx8mm_uid>; > > nvmem-cell-names = "soc_unique_id"; > > > > -- > > 2.29.2 > > > > > > _______________________________________________ > > linux-arm-kernel mailing list > > linux-arm-kernel@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >
On Wed, May 5, 2021 at 6:54 AM Lucas Stach <l.stach@pengutronix.de> wrote: > > Am Mittwoch, dem 05.05.2021 um 06:36 -0500 schrieb Adam Ford: > > On Tue, May 4, 2021 at 3:21 AM Lucas Stach <l.stach@pengutronix.de> wrote: > > > > > > DMA addressing capabilities on i.MX8MM are limited by the interconnect, > > > same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let > > > the kernel know about this. > > > > Can you point me to the section of the reference manual where this is > > found? I'm guessing a similar thing would be applicable to the 8M > > Nano as well, but I want to understand first. > > The second patch in this series already fixes up the 8MN DT. Thanks, I didn't even notice there was a 2/2 patch. My mistake. Sorry for the noise. > > The relevant part of the RM is section 2.1.2 (Cortex-A53 memory map) > where you can see that the DDR above the 4GB mark is only accessible to > the A53 cluster, other DMA masters only have access to the 3GB located > below the 4GB mark. Thanks for the clarification. adam > > Regards, > Lucas > > > thanks > > > > adam > > > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > > --- > > > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 + > > > 1 file changed, 1 insertion(+) > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > > index 6bf1d15ba16a..5bdc730f6132 100644 > > > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > > @@ -261,6 +261,7 @@ soc@0 { > > > #address-cells = <1>; > > > #size-cells = <1>; > > > ranges = <0x0 0x0 0x0 0x3e000000>; > > > + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; > > > nvmem-cells = <&imx8mm_uid>; > > > nvmem-cell-names = "soc_unique_id"; > > > > > > -- > > > 2.29.2 > > > > > > > > > _______________________________________________ > > > linux-arm-kernel mailing list > > > linux-arm-kernel@lists.infradead.org > > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > > >
On Tue, May 04, 2021 at 10:20:51AM +0200, Lucas Stach wrote: > DMA addressing capabilities on i.MX8MM are limited by the interconnect, > same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let > the kernel know about this. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Applied both, thanks.
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 6bf1d15ba16a..5bdc730f6132 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -261,6 +261,7 @@ soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; nvmem-cells = <&imx8mm_uid>; nvmem-cell-names = "soc_unique_id";
DMA addressing capabilities on i.MX8MM are limited by the interconnect, same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let the kernel know about this. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 + 1 file changed, 1 insertion(+)