| Message ID | 20210524134517.687089-1-martin.blumenstingl@googlemail.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | [v2] clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_sel | expand |
On Mon 24 May 2021 at 15:45, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: > Use CLK_SET_RATE_NO_REPARENT for the vclk{,2}_in_sel clocks. The only > parent which is actually used is vid_pll_final_div. This should be set > using assigned-clock-parents in the .dts rather than removing some > "unwanted" clock parents from the clock driver. > > Suggested-by: Jerome Brunet <jbrunet@baylibre.com> > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > --- > After a hint from Jerome (thanks) this is the improved version of > "clk: meson: meson8b: Don't use MPLL1 as parent of vclk_in_sel" from [0] > > > [0] https://patchwork.kernel.org/project/linux-clk/patch/20210524104533.555953-1-martin.blumenstingl@googlemail.com/ > > > drivers/clk/meson/meson8b.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c > index a844d35b553a..0f8bd707217a 100644 > --- a/drivers/clk/meson/meson8b.c > +++ b/drivers/clk/meson/meson8b.c > @@ -1175,7 +1175,7 @@ static struct clk_regmap meson8b_vclk_in_sel = { > .ops = &clk_regmap_mux_ro_ops, I just noticed that these muxes are read-only ATM. It does not make this change (or the previous one) wrong but it does not make much sense as the mux won't ever change. I suppose you make this mutable with another patch later on ? > .parent_hws = meson8b_vclk_mux_parent_hws, > .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws), > - .flags = CLK_SET_RATE_PARENT, > + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, > }, > }; > > @@ -1358,7 +1358,7 @@ static struct clk_regmap meson8b_vclk2_in_sel = { > .ops = &clk_regmap_mux_ro_ops, > .parent_hws = meson8b_vclk_mux_parent_hws, > .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws), > - .flags = CLK_SET_RATE_PARENT, > + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, > }, > };
Hi Jerome, On Mon, May 24, 2021 at 4:30 PM Jerome Brunet <jbrunet@baylibre.com> wrote: > > > On Mon 24 May 2021 at 15:45, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: > > > Use CLK_SET_RATE_NO_REPARENT for the vclk{,2}_in_sel clocks. The only > > parent which is actually used is vid_pll_final_div. This should be set > > using assigned-clock-parents in the .dts rather than removing some > > "unwanted" clock parents from the clock driver. > > > > Suggested-by: Jerome Brunet <jbrunet@baylibre.com> > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > > --- > > After a hint from Jerome (thanks) this is the improved version of > > "clk: meson: meson8b: Don't use MPLL1 as parent of vclk_in_sel" from [0] > > > > > > [0] https://patchwork.kernel.org/project/linux-clk/patch/20210524104533.555953-1-martin.blumenstingl@googlemail.com/ > > > > > > drivers/clk/meson/meson8b.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c > > index a844d35b553a..0f8bd707217a 100644 > > --- a/drivers/clk/meson/meson8b.c > > +++ b/drivers/clk/meson/meson8b.c > > @@ -1175,7 +1175,7 @@ static struct clk_regmap meson8b_vclk_in_sel = { > > .ops = &clk_regmap_mux_ro_ops, > > I just noticed that these muxes are read-only ATM. > It does not make this change (or the previous one) wrong but it does not > make much sense as the mux won't ever change. indeed, as-is the patch is a no-op > I suppose you make this mutable with another patch later on ? correct, I have a patch in my queue which will make all relevant clocks in the vclk and vclk2 trees mutable my idea behind this is to not mix any _ro_ops to _ops conversion with other types of changes (so the actual reason for a change is still documented in the git history) Best regards, Martin
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index a844d35b553a..0f8bd707217a 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -1175,7 +1175,7 @@ static struct clk_regmap meson8b_vclk_in_sel = { .ops = &clk_regmap_mux_ro_ops, .parent_hws = meson8b_vclk_mux_parent_hws, .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, }, }; @@ -1358,7 +1358,7 @@ static struct clk_regmap meson8b_vclk2_in_sel = { .ops = &clk_regmap_mux_ro_ops, .parent_hws = meson8b_vclk_mux_parent_hws, .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, }, };
Use CLK_SET_RATE_NO_REPARENT for the vclk{,2}_in_sel clocks. The only parent which is actually used is vid_pll_final_div. This should be set using assigned-clock-parents in the .dts rather than removing some "unwanted" clock parents from the clock driver. Suggested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- After a hint from Jerome (thanks) this is the improved version of "clk: meson: meson8b: Don't use MPLL1 as parent of vclk_in_sel" from [0] [0] https://patchwork.kernel.org/project/linux-clk/patch/20210524104533.555953-1-martin.blumenstingl@googlemail.com/ drivers/clk/meson/meson8b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)