| Message ID | 20210605030915.411391-1-xieqinick@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: meson: vim3l: add NNA node | expand |
Hi Nick, On Sat, Jun 5, 2021 at 5:09 AM <xieqinick@gmail.com> wrote: > > From: Nick Xie <nick@khadas.com> > > Add Neural Network Accelerator device tree node > for Khadas VIM3L. we neither have a driver for this upstream nor any binding documentation in Documentation/devicetree/bindings/ are you planning to add this? Especially the missing binding documentation is problematic as it causes some warnings when validating the .dts files against the bindings from Documentation/devicetree/bindings/ Best regards, Martin
Hi, On 05/06/2021 11:49, Martin Blumenstingl wrote: > Hi Nick, > > On Sat, Jun 5, 2021 at 5:09 AM <xieqinick@gmail.com> wrote: >> >> From: Nick Xie <nick@khadas.com> >> >> Add Neural Network Accelerator device tree node >> for Khadas VIM3L. > we neither have a driver for this upstream nor any binding > documentation in Documentation/devicetree/bindings/ > are you planning to add this? > > Especially the missing binding documentation is problematic as it > causes some warnings when validating the .dts files against the > bindings from Documentation/devicetree/bindings/ Actually the NNA core is a verisilicon VIVANTE core, but I have no idea what is the difference with the VIVANTE GPU cores ? the userspace libraries & SDK shipped by Amlogic exposes OpenCL and (AFAIK) NNA over OpenCL, so I think the HW description should be similar to the current Etnaviv bindings. Neil > > > Best regards, > Martin >
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts index 06de0b1ce726..8a4abb61432e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts @@ -14,6 +14,29 @@ / { compatible = "khadas,vim3l", "amlogic,sm1"; model = "Khadas VIM3L"; + galcore { + compatible = "amlogic, galcore"; + dev_name = "galcore"; + status = "okay"; + clocks = <&clkc CLKID_NNA_AXI_CLK>, + <&clkc CLKID_NNA_CORE_CLK>; + clock-names = "cts_vipnanoq_axi_clk_composite", + "cts_vipnanoq_core_clk_composite"; + interrupts = <0 186 4>; + interrupt-names = "galcore"; + reg = <0x0 0xff100000 0x0 0x800 + 0x0 0xff000000 0x0 0x400000 + 0x0 0xff63c118 0x0 0x0 + 0x0 0xff63c11c 0x0 0x0 + 0x0 0xffd01088 0x0 0x0 + 0x0 0xff63c1c8 0x0 0x0 + >; + reg-names = "NN_REG","NN_SRAM","NN_MEM0", + "NN_MEM1","NN_RESET","NN_CLK"; + nn_power_version = <3>; + nn_efuse = <0xff63003c 0x20>; + }; + vddcpu: regulator-vddcpu { /* * Silergy SY8030DEC Regulator.