diff mbox series

[3/3] drm/i915/uapi: Add query for L3 bank count

Message ID 20210610204626.2995262-4-John.C.Harrison@Intel.com (mailing list archive)
State New, archived
Headers show
Series Add support for querying hw info that UMDs need | expand

Commit Message

John Harrison June 10, 2021, 8:46 p.m. UTC 
From: John Harrison <John.C.Harrison@Intel.com>

Various UMDs need to know the L3 bank count. So add a query API for it.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt.c | 15 +++++++++++++++
 drivers/gpu/drm/i915/gt/intel_gt.h |  1 +
 drivers/gpu/drm/i915/i915_query.c  | 22 ++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h    |  1 +
 include/uapi/drm/i915_drm.h        |  1 +
 5 files changed, 40 insertions(+)

Comments

Matthew Brost June 10, 2021, 10:09 p.m. UTC | #1 
On Thu, Jun 10, 2021 at 01:46:26PM -0700, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
> 
> Various UMDs need to know the L3 bank count. So add a query API for it.
> 
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt.c | 15 +++++++++++++++
>  drivers/gpu/drm/i915/gt/intel_gt.h |  1 +
>  drivers/gpu/drm/i915/i915_query.c  | 22 ++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h    |  1 +
>  include/uapi/drm/i915_drm.h        |  1 +
>  5 files changed, 40 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 2161bf01ef8b..708bb3581d83 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -704,3 +704,18 @@ void intel_gt_info_print(const struct intel_gt_info *info,
>  
>  	intel_sseu_dump(&info->sseu, p);
>  }
> +
> +int intel_gt_get_l3bank_count(struct intel_gt *gt)

Small nit, this function is ..'l3bank_count' while the define for query
is ..'L3_BANK_COUNT'. I'm thinking this function should have a space
between l3 & bank for consistency.

> +{
> +	struct drm_i915_private *i915 = gt->i915;
> +	intel_wakeref_t wakeref;
> +	u32 fuse3;
> +
> +	if (GRAPHICS_VER(i915) < 12)
> +		return -ENODEV;
> +
> +	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> +		fuse3 = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
> +
> +	return hweight32(REG_FIELD_GET(GEN12_GT_L3_MODE_MASK, ~fuse3));
> +}
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index 7ec395cace69..46aa1cf4cf30 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -77,6 +77,7 @@ static inline bool intel_gt_is_wedged(const struct intel_gt *gt)
>  
>  void intel_gt_info_print(const struct intel_gt_info *info,
>  			 struct drm_printer *p);
> +int intel_gt_get_l3bank_count(struct intel_gt *gt);
>  
>  void intel_gt_watchdog_work(struct work_struct *work);
>  
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 96bd8fb3e895..0e92bb2d21b2 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -10,6 +10,7 @@
>  #include "i915_perf.h"
>  #include "i915_query.h"
>  #include <uapi/drm/i915_drm.h>
> +#include "gt/intel_gt.h"
>  
>  static int copy_query_item(void *query_hdr, size_t query_sz,
>  			   u32 total_length,
> @@ -502,6 +503,26 @@ static int query_hwconfig_table(struct drm_i915_private *i915,
>  	return hwconfig->size;
>  }
>  
> +static int query_l3banks(struct drm_i915_private *i915,
> +			 struct drm_i915_query_item *query_item)
> +{
> +	u32 banks;
> +
> +	if (query_item->length == 0)
> +		return sizeof(banks);
> +
> +	if (query_item->length < sizeof(banks))
> +		return -EINVAL;
> +
> +	banks = intel_gt_get_l3bank_count(&i915->gt);
> +
> +	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
> +			 &banks, sizeof(banks)))
> +		return -EFAULT;
> +
> +	return sizeof(banks);
> +}
> +
>  static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
>  					struct drm_i915_query_item *query_item) = {
>  	query_topology_info,
> @@ -509,6 +530,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
>  	query_perf_config,
>  	query_memregion_info,
>  	query_hwconfig_table,
> +	query_l3banks,

Another nit, for consistency query_l3banks -> query_l3_bank_count.

With these nits fixed:
Reviewed-by: Matthew Brost <matthew.brost@intel.com>

>  };
>  
>  int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eb13c601d680..e9ba88fe3db7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3099,6 +3099,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
>  #define GEN10_L3BANK_PAIR_COUNT     4
>  #define GEN10_L3BANK_MASK   0x0F
> +#define GEN12_GT_L3_MODE_MASK 0xFF
>  
>  #define GEN8_EU_DISABLE0		_MMIO(0x9134)
>  #define   GEN8_EU_DIS0_S0_MASK		0xffffff
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 87d369cae22a..20d18cca5066 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -2234,6 +2234,7 @@ struct drm_i915_query_item {
>  #define DRM_I915_QUERY_PERF_CONFIG      3
>  #define DRM_I915_QUERY_MEMORY_REGIONS   4
>  #define DRM_I915_QUERY_HWCONFIG_TABLE   5
> +#define DRM_I915_QUERY_L3_BANK_COUNT    6
>  /* Must be kept compact -- no holes and well documented */
>  
>  	/**
> -- 
> 2.25.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Michal Wajdeczko June 10, 2021, 11:03 p.m. UTC | #2 
On 10.06.2021 22:46, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
> 
> Various UMDs need to know the L3 bank count. So add a query API for it.
> 
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt.c | 15 +++++++++++++++
>  drivers/gpu/drm/i915/gt/intel_gt.h |  1 +
>  drivers/gpu/drm/i915/i915_query.c  | 22 ++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h    |  1 +
>  include/uapi/drm/i915_drm.h        |  1 +
>  5 files changed, 40 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 2161bf01ef8b..708bb3581d83 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -704,3 +704,18 @@ void intel_gt_info_print(const struct intel_gt_info *info,
>  
>  	intel_sseu_dump(&info->sseu, p);
>  }
> +
> +int intel_gt_get_l3bank_count(struct intel_gt *gt)
> +{
> +	struct drm_i915_private *i915 = gt->i915;
> +	intel_wakeref_t wakeref;
> +	u32 fuse3;
> +
> +	if (GRAPHICS_VER(i915) < 12)
> +		return -ENODEV;
> +
> +	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> +		fuse3 = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
> +
> +	return hweight32(REG_FIELD_GET(GEN12_GT_L3_MODE_MASK, ~fuse3));
> +}
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index 7ec395cace69..46aa1cf4cf30 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -77,6 +77,7 @@ static inline bool intel_gt_is_wedged(const struct intel_gt *gt)
>  
>  void intel_gt_info_print(const struct intel_gt_info *info,
>  			 struct drm_printer *p);
> +int intel_gt_get_l3bank_count(struct intel_gt *gt);
>  
>  void intel_gt_watchdog_work(struct work_struct *work);
>  
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 96bd8fb3e895..0e92bb2d21b2 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -10,6 +10,7 @@
>  #include "i915_perf.h"
>  #include "i915_query.h"
>  #include <uapi/drm/i915_drm.h>
> +#include "gt/intel_gt.h"
>  
>  static int copy_query_item(void *query_hdr, size_t query_sz,
>  			   u32 total_length,
> @@ -502,6 +503,26 @@ static int query_hwconfig_table(struct drm_i915_private *i915,
>  	return hwconfig->size;
>  }
>  
> +static int query_l3banks(struct drm_i915_private *i915,
> +			 struct drm_i915_query_item *query_item)
> +{
> +	u32 banks;

likely we also need to check:

	if (query_item->flags != 0)
		return -EINVAL;

> +
> +	if (query_item->length == 0)
> +		return sizeof(banks);
> +
> +	if (query_item->length < sizeof(banks))
> +		return -EINVAL;
> +
> +	banks = intel_gt_get_l3bank_count(&i915->gt);
> +
> +	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
> +			 &banks, sizeof(banks)))
> +		return -EFAULT;
> +
> +	return sizeof(banks);
> +}
> +
>  static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
>  					struct drm_i915_query_item *query_item) = {
>  	query_topology_info,
> @@ -509,6 +530,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
>  	query_perf_config,
>  	query_memregion_info,
>  	query_hwconfig_table,
> +	query_l3banks,
>  };
>  
>  int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eb13c601d680..e9ba88fe3db7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3099,6 +3099,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
>  #define GEN10_L3BANK_PAIR_COUNT     4
>  #define GEN10_L3BANK_MASK   0x0F
> +#define GEN12_GT_L3_MODE_MASK 0xFF
>  
>  #define GEN8_EU_DISABLE0		_MMIO(0x9134)
>  #define   GEN8_EU_DIS0_S0_MASK		0xffffff
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 87d369cae22a..20d18cca5066 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -2234,6 +2234,7 @@ struct drm_i915_query_item {
>  #define DRM_I915_QUERY_PERF_CONFIG      3
>  #define DRM_I915_QUERY_MEMORY_REGIONS   4
>  #define DRM_I915_QUERY_HWCONFIG_TABLE   5
> +#define DRM_I915_QUERY_L3_BANK_COUNT    6
>  /* Must be kept compact -- no holes and well documented */
>  
>  	/**
>
Lionel Landwerlin June 11, 2021, 6:03 a.m. UTC | #3 
On 10/06/2021 23:46, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Various UMDs need to know the L3 bank count. So add a query API for it.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_gt.c | 15 +++++++++++++++
>   drivers/gpu/drm/i915/gt/intel_gt.h |  1 +
>   drivers/gpu/drm/i915/i915_query.c  | 22 ++++++++++++++++++++++
>   drivers/gpu/drm/i915/i915_reg.h    |  1 +
>   include/uapi/drm/i915_drm.h        |  1 +
>   5 files changed, 40 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 2161bf01ef8b..708bb3581d83 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -704,3 +704,18 @@ void intel_gt_info_print(const struct intel_gt_info *info,
>   
>   	intel_sseu_dump(&info->sseu, p);
>   }
> +
> +int intel_gt_get_l3bank_count(struct intel_gt *gt)
> +{
> +	struct drm_i915_private *i915 = gt->i915;
> +	intel_wakeref_t wakeref;
> +	u32 fuse3;
> +
> +	if (GRAPHICS_VER(i915) < 12)
> +		return -ENODEV;
> +
> +	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> +		fuse3 = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
> +
> +	return hweight32(REG_FIELD_GET(GEN12_GT_L3_MODE_MASK, ~fuse3));
> +}
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index 7ec395cace69..46aa1cf4cf30 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -77,6 +77,7 @@ static inline bool intel_gt_is_wedged(const struct intel_gt *gt)
>   
>   void intel_gt_info_print(const struct intel_gt_info *info,
>   			 struct drm_printer *p);
> +int intel_gt_get_l3bank_count(struct intel_gt *gt);
>   
>   void intel_gt_watchdog_work(struct work_struct *work);
>   
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 96bd8fb3e895..0e92bb2d21b2 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -10,6 +10,7 @@
>   #include "i915_perf.h"
>   #include "i915_query.h"
>   #include <uapi/drm/i915_drm.h>
> +#include "gt/intel_gt.h"
>   
>   static int copy_query_item(void *query_hdr, size_t query_sz,
>   			   u32 total_length,
> @@ -502,6 +503,26 @@ static int query_hwconfig_table(struct drm_i915_private *i915,
>   	return hwconfig->size;
>   }
>   
> +static int query_l3banks(struct drm_i915_private *i915,
> +			 struct drm_i915_query_item *query_item)
> +{
> +	u32 banks;
> +
> +	if (query_item->length == 0)
> +		return sizeof(banks);
> +
> +	if (query_item->length < sizeof(banks))
> +		return -EINVAL;
> +
> +	banks = intel_gt_get_l3bank_count(&i915->gt);
> +
> +	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
> +			 &banks, sizeof(banks)))
> +		return -EFAULT;
> +
> +	return sizeof(banks);
> +}
> +
>   static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
>   					struct drm_i915_query_item *query_item) = {
>   	query_topology_info,
> @@ -509,6 +530,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
>   	query_perf_config,
>   	query_memregion_info,
>   	query_hwconfig_table,
> +	query_l3banks,
>   };
>   
>   int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eb13c601d680..e9ba88fe3db7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3099,6 +3099,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>   #define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
>   #define GEN10_L3BANK_PAIR_COUNT     4
>   #define GEN10_L3BANK_MASK   0x0F
> +#define GEN12_GT_L3_MODE_MASK 0xFF
>   
>   #define GEN8_EU_DISABLE0		_MMIO(0x9134)
>   #define   GEN8_EU_DIS0_S0_MASK		0xffffff
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 87d369cae22a..20d18cca5066 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -2234,6 +2234,7 @@ struct drm_i915_query_item {
>   #define DRM_I915_QUERY_PERF_CONFIG      3
>   #define DRM_I915_QUERY_MEMORY_REGIONS   4
>   #define DRM_I915_QUERY_HWCONFIG_TABLE   5
> +#define DRM_I915_QUERY_L3_BANK_COUNT    6


A little bit of documentation about the format of the return data would 
be nice :)


-Lionel


>   /* Must be kept compact -- no holes and well documented */
>   
>   	/**
Tvrtko Ursulin June 16, 2021, 10:08 a.m. UTC | #4 
On 10/06/2021 21:46, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
> 
> Various UMDs need to know the L3 bank count. So add a query API for it.
> 
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_gt.c | 15 +++++++++++++++
>   drivers/gpu/drm/i915/gt/intel_gt.h |  1 +
>   drivers/gpu/drm/i915/i915_query.c  | 22 ++++++++++++++++++++++
>   drivers/gpu/drm/i915/i915_reg.h    |  1 +
>   include/uapi/drm/i915_drm.h        |  1 +
>   5 files changed, 40 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 2161bf01ef8b..708bb3581d83 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -704,3 +704,18 @@ void intel_gt_info_print(const struct intel_gt_info *info,
>   
>   	intel_sseu_dump(&info->sseu, p);
>   }
> +
> +int intel_gt_get_l3bank_count(struct intel_gt *gt)
> +{
> +	struct drm_i915_private *i915 = gt->i915;
> +	intel_wakeref_t wakeref;
> +	u32 fuse3;
> +
> +	if (GRAPHICS_VER(i915) < 12)
> +		return -ENODEV;
> +
> +	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> +		fuse3 = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
> +
> +	return hweight32(REG_FIELD_GET(GEN12_GT_L3_MODE_MASK, ~fuse3));
> +}
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index 7ec395cace69..46aa1cf4cf30 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -77,6 +77,7 @@ static inline bool intel_gt_is_wedged(const struct intel_gt *gt)
>   
>   void intel_gt_info_print(const struct intel_gt_info *info,
>   			 struct drm_printer *p);
> +int intel_gt_get_l3bank_count(struct intel_gt *gt);
>   
>   void intel_gt_watchdog_work(struct work_struct *work);
>   
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 96bd8fb3e895..0e92bb2d21b2 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -10,6 +10,7 @@
>   #include "i915_perf.h"
>   #include "i915_query.h"
>   #include <uapi/drm/i915_drm.h>
> +#include "gt/intel_gt.h"
>   
>   static int copy_query_item(void *query_hdr, size_t query_sz,
>   			   u32 total_length,
> @@ -502,6 +503,26 @@ static int query_hwconfig_table(struct drm_i915_private *i915,
>   	return hwconfig->size;
>   }
>   
> +static int query_l3banks(struct drm_i915_private *i915,
> +			 struct drm_i915_query_item *query_item)
> +{
> +	u32 banks;
> +
> +	if (query_item->length == 0)
> +		return sizeof(banks);
> +
> +	if (query_item->length < sizeof(banks))
> +		return -EINVAL;
> +
> +	banks = intel_gt_get_l3bank_count(&i915->gt);

Having spotted i915->gt I am thinking whether this should be future 
proofed to take, say, struct i915_engine_class_instance as input. If one 
need different GTs will have different L3 config. Alternative is adding 
a new query at that point. No strong opinion either way.

Otherwise yes, I agree with adding flags mbz check and documenting the 
uapi as other people have suggested.

Regards,

Tvrtko

> +
> +	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
> +			 &banks, sizeof(banks)))
> +		return -EFAULT;
> +
> +	return sizeof(banks);
> +}
> +
>   static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
>   					struct drm_i915_query_item *query_item) = {
>   	query_topology_info,
> @@ -509,6 +530,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
>   	query_perf_config,
>   	query_memregion_info,
>   	query_hwconfig_table,
> +	query_l3banks,
>   };
>   
>   int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eb13c601d680..e9ba88fe3db7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3099,6 +3099,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>   #define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
>   #define GEN10_L3BANK_PAIR_COUNT     4
>   #define GEN10_L3BANK_MASK   0x0F
> +#define GEN12_GT_L3_MODE_MASK 0xFF
>   
>   #define GEN8_EU_DISABLE0		_MMIO(0x9134)
>   #define   GEN8_EU_DIS0_S0_MASK		0xffffff
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 87d369cae22a..20d18cca5066 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -2234,6 +2234,7 @@ struct drm_i915_query_item {
>   #define DRM_I915_QUERY_PERF_CONFIG      3
>   #define DRM_I915_QUERY_MEMORY_REGIONS   4
>   #define DRM_I915_QUERY_HWCONFIG_TABLE   5
> +#define DRM_I915_QUERY_L3_BANK_COUNT    6
>   /* Must be kept compact -- no holes and well documented */
>   
>   	/**
>
Daniel Vetter June 16, 2021, 10:25 a.m. UTC | #5 
On Thu, Jun 10, 2021 at 10:46 PM <John.C.Harrison@intel.com> wrote:
>
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Various UMDs need to know the L3 bank count. So add a query API for it.

Please link to both the igt test submission for this (there's not even
a Test-with: on the cover letter) and the merge requests for the
various UMD which uses new uapi. Also as other mentioned, full uapi
kerneldoc is needed too. Please fill in any gaps in the existing docs
that relate to your addition directly (like we've e.g. done for the
extension chaining when adding lmem support).

Thanks, Daniel

>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt.c | 15 +++++++++++++++
>  drivers/gpu/drm/i915/gt/intel_gt.h |  1 +
>  drivers/gpu/drm/i915/i915_query.c  | 22 ++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h    |  1 +
>  include/uapi/drm/i915_drm.h        |  1 +
>  5 files changed, 40 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 2161bf01ef8b..708bb3581d83 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -704,3 +704,18 @@ void intel_gt_info_print(const struct intel_gt_info *info,
>
>         intel_sseu_dump(&info->sseu, p);
>  }
> +
> +int intel_gt_get_l3bank_count(struct intel_gt *gt)
> +{
> +       struct drm_i915_private *i915 = gt->i915;
> +       intel_wakeref_t wakeref;
> +       u32 fuse3;
> +
> +       if (GRAPHICS_VER(i915) < 12)
> +               return -ENODEV;
> +
> +       with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> +               fuse3 = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
> +
> +       return hweight32(REG_FIELD_GET(GEN12_GT_L3_MODE_MASK, ~fuse3));
> +}
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index 7ec395cace69..46aa1cf4cf30 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -77,6 +77,7 @@ static inline bool intel_gt_is_wedged(const struct intel_gt *gt)
>
>  void intel_gt_info_print(const struct intel_gt_info *info,
>                          struct drm_printer *p);
> +int intel_gt_get_l3bank_count(struct intel_gt *gt);
>
>  void intel_gt_watchdog_work(struct work_struct *work);
>
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 96bd8fb3e895..0e92bb2d21b2 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -10,6 +10,7 @@
>  #include "i915_perf.h"
>  #include "i915_query.h"
>  #include <uapi/drm/i915_drm.h>
> +#include "gt/intel_gt.h"
>
>  static int copy_query_item(void *query_hdr, size_t query_sz,
>                            u32 total_length,
> @@ -502,6 +503,26 @@ static int query_hwconfig_table(struct drm_i915_private *i915,
>         return hwconfig->size;
>  }
>
> +static int query_l3banks(struct drm_i915_private *i915,
> +                        struct drm_i915_query_item *query_item)
> +{
> +       u32 banks;
> +
> +       if (query_item->length == 0)
> +               return sizeof(banks);
> +
> +       if (query_item->length < sizeof(banks))
> +               return -EINVAL;
> +
> +       banks = intel_gt_get_l3bank_count(&i915->gt);
> +
> +       if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
> +                        &banks, sizeof(banks)))
> +               return -EFAULT;
> +
> +       return sizeof(banks);
> +}
> +
>  static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
>                                         struct drm_i915_query_item *query_item) = {
>         query_topology_info,
> @@ -509,6 +530,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
>         query_perf_config,
>         query_memregion_info,
>         query_hwconfig_table,
> +       query_l3banks,
>  };
>
>  int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eb13c601d680..e9ba88fe3db7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3099,6 +3099,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define        GEN10_MIRROR_FUSE3              _MMIO(0x9118)
>  #define GEN10_L3BANK_PAIR_COUNT     4
>  #define GEN10_L3BANK_MASK   0x0F
> +#define GEN12_GT_L3_MODE_MASK 0xFF
>
>  #define GEN8_EU_DISABLE0               _MMIO(0x9134)
>  #define   GEN8_EU_DIS0_S0_MASK         0xffffff
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 87d369cae22a..20d18cca5066 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -2234,6 +2234,7 @@ struct drm_i915_query_item {
>  #define DRM_I915_QUERY_PERF_CONFIG      3
>  #define DRM_I915_QUERY_MEMORY_REGIONS   4
>  #define DRM_I915_QUERY_HWCONFIG_TABLE   5
> +#define DRM_I915_QUERY_L3_BANK_COUNT    6
>  /* Must be kept compact -- no holes and well documented */
>
>         /**
> --
> 2.25.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
John Harrison July 15, 2021, 10:16 p.m. UTC | #6 
On 6/16/2021 03:25, Daniel Vetter wrote:
> On Thu, Jun 10, 2021 at 10:46 PM <John.C.Harrison@intel.com> wrote:
>> From: John Harrison <John.C.Harrison@Intel.com>
>>
>> Various UMDs need to know the L3 bank count. So add a query API for it.
> Please link to both the igt test submission for this (there's not even
> a Test-with: on the cover letter)
Is there a wiki page that describes all such tags? That is not one I was 
aware of and I can't find anything in the Kernel patch submission wiki 
or DRM maintainers wiki that mentions it.


>   and the merge requests for the
> various UMD which uses new uapi.
Is there a particular tag to use for this?

John.

>   Also as other mentioned, full uapi
> kerneldoc is needed too. Please fill in any gaps in the existing docs
> that relate to your addition directly (like we've e.g. done for the
> extension chaining when adding lmem support).
>
> Thanks, Daniel
>
>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_gt.c | 15 +++++++++++++++
>>   drivers/gpu/drm/i915/gt/intel_gt.h |  1 +
>>   drivers/gpu/drm/i915/i915_query.c  | 22 ++++++++++++++++++++++
>>   drivers/gpu/drm/i915/i915_reg.h    |  1 +
>>   include/uapi/drm/i915_drm.h        |  1 +
>>   5 files changed, 40 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
>> index 2161bf01ef8b..708bb3581d83 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>> @@ -704,3 +704,18 @@ void intel_gt_info_print(const struct intel_gt_info *info,
>>
>>          intel_sseu_dump(&info->sseu, p);
>>   }
>> +
>> +int intel_gt_get_l3bank_count(struct intel_gt *gt)
>> +{
>> +       struct drm_i915_private *i915 = gt->i915;
>> +       intel_wakeref_t wakeref;
>> +       u32 fuse3;
>> +
>> +       if (GRAPHICS_VER(i915) < 12)
>> +               return -ENODEV;
>> +
>> +       with_intel_runtime_pm(gt->uncore->rpm, wakeref)
>> +               fuse3 = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
>> +
>> +       return hweight32(REG_FIELD_GET(GEN12_GT_L3_MODE_MASK, ~fuse3));
>> +}
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
>> index 7ec395cace69..46aa1cf4cf30 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
>> @@ -77,6 +77,7 @@ static inline bool intel_gt_is_wedged(const struct intel_gt *gt)
>>
>>   void intel_gt_info_print(const struct intel_gt_info *info,
>>                           struct drm_printer *p);
>> +int intel_gt_get_l3bank_count(struct intel_gt *gt);
>>
>>   void intel_gt_watchdog_work(struct work_struct *work);
>>
>> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
>> index 96bd8fb3e895..0e92bb2d21b2 100644
>> --- a/drivers/gpu/drm/i915/i915_query.c
>> +++ b/drivers/gpu/drm/i915/i915_query.c
>> @@ -10,6 +10,7 @@
>>   #include "i915_perf.h"
>>   #include "i915_query.h"
>>   #include <uapi/drm/i915_drm.h>
>> +#include "gt/intel_gt.h"
>>
>>   static int copy_query_item(void *query_hdr, size_t query_sz,
>>                             u32 total_length,
>> @@ -502,6 +503,26 @@ static int query_hwconfig_table(struct drm_i915_private *i915,
>>          return hwconfig->size;
>>   }
>>
>> +static int query_l3banks(struct drm_i915_private *i915,
>> +                        struct drm_i915_query_item *query_item)
>> +{
>> +       u32 banks;
>> +
>> +       if (query_item->length == 0)
>> +               return sizeof(banks);
>> +
>> +       if (query_item->length < sizeof(banks))
>> +               return -EINVAL;
>> +
>> +       banks = intel_gt_get_l3bank_count(&i915->gt);
>> +
>> +       if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
>> +                        &banks, sizeof(banks)))
>> +               return -EFAULT;
>> +
>> +       return sizeof(banks);
>> +}
>> +
>>   static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
>>                                          struct drm_i915_query_item *query_item) = {
>>          query_topology_info,
>> @@ -509,6 +530,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
>>          query_perf_config,
>>          query_memregion_info,
>>          query_hwconfig_table,
>> +       query_l3banks,
>>   };
>>
>>   int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index eb13c601d680..e9ba88fe3db7 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -3099,6 +3099,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>>   #define        GEN10_MIRROR_FUSE3              _MMIO(0x9118)
>>   #define GEN10_L3BANK_PAIR_COUNT     4
>>   #define GEN10_L3BANK_MASK   0x0F
>> +#define GEN12_GT_L3_MODE_MASK 0xFF
>>
>>   #define GEN8_EU_DISABLE0               _MMIO(0x9134)
>>   #define   GEN8_EU_DIS0_S0_MASK         0xffffff
>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
>> index 87d369cae22a..20d18cca5066 100644
>> --- a/include/uapi/drm/i915_drm.h
>> +++ b/include/uapi/drm/i915_drm.h
>> @@ -2234,6 +2234,7 @@ struct drm_i915_query_item {
>>   #define DRM_I915_QUERY_PERF_CONFIG      3
>>   #define DRM_I915_QUERY_MEMORY_REGIONS   4
>>   #define DRM_I915_QUERY_HWCONFIG_TABLE   5
>> +#define DRM_I915_QUERY_L3_BANK_COUNT    6
>>   /* Must be kept compact -- no holes and well documented */
>>
>>          /**
>> --
>> 2.25.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
Daniel Vetter July 20, 2021, 12:58 p.m. UTC | #7 
On Thu, Jul 15, 2021 at 03:16:08PM -0700, John Harrison wrote:
> On 6/16/2021 03:25, Daniel Vetter wrote:
> > On Thu, Jun 10, 2021 at 10:46 PM <John.C.Harrison@intel.com> wrote:
> > > From: John Harrison <John.C.Harrison@Intel.com>
> > > 
> > > Various UMDs need to know the L3 bank count. So add a query API for it.
> > Please link to both the igt test submission for this (there's not even
> > a Test-with: on the cover letter)
> Is there a wiki page that describes all such tags? That is not one I was
> aware of and I can't find anything in the Kernel patch submission wiki or
> DRM maintainers wiki that mentions it.

It's in the CI docs (linked from the main page too)

https://intel-gfx-ci.01.org/test-with.html

> >   and the merge requests for the
> > various UMD which uses new uapi.
> Is there a particular tag to use for this?

I think often just a link to the merge request in the cover letter.
Sometimes people also put the link in the uapi patch itself in the commit
message. Which I think would be best.
-Daniel



> 
> John.
> 
> >   Also as other mentioned, full uapi
> > kerneldoc is needed too. Please fill in any gaps in the existing docs
> > that relate to your addition directly (like we've e.g. done for the
> > extension chaining when adding lmem support).
> > 
> > Thanks, Daniel
> > 
> > > Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> > > ---
> > >   drivers/gpu/drm/i915/gt/intel_gt.c | 15 +++++++++++++++
> > >   drivers/gpu/drm/i915/gt/intel_gt.h |  1 +
> > >   drivers/gpu/drm/i915/i915_query.c  | 22 ++++++++++++++++++++++
> > >   drivers/gpu/drm/i915/i915_reg.h    |  1 +
> > >   include/uapi/drm/i915_drm.h        |  1 +
> > >   5 files changed, 40 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > index 2161bf01ef8b..708bb3581d83 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > @@ -704,3 +704,18 @@ void intel_gt_info_print(const struct intel_gt_info *info,
> > > 
> > >          intel_sseu_dump(&info->sseu, p);
> > >   }
> > > +
> > > +int intel_gt_get_l3bank_count(struct intel_gt *gt)
> > > +{
> > > +       struct drm_i915_private *i915 = gt->i915;
> > > +       intel_wakeref_t wakeref;
> > > +       u32 fuse3;
> > > +
> > > +       if (GRAPHICS_VER(i915) < 12)
> > > +               return -ENODEV;
> > > +
> > > +       with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> > > +               fuse3 = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
> > > +
> > > +       return hweight32(REG_FIELD_GET(GEN12_GT_L3_MODE_MASK, ~fuse3));
> > > +}
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> > > index 7ec395cace69..46aa1cf4cf30 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> > > @@ -77,6 +77,7 @@ static inline bool intel_gt_is_wedged(const struct intel_gt *gt)
> > > 
> > >   void intel_gt_info_print(const struct intel_gt_info *info,
> > >                           struct drm_printer *p);
> > > +int intel_gt_get_l3bank_count(struct intel_gt *gt);
> > > 
> > >   void intel_gt_watchdog_work(struct work_struct *work);
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> > > index 96bd8fb3e895..0e92bb2d21b2 100644
> > > --- a/drivers/gpu/drm/i915/i915_query.c
> > > +++ b/drivers/gpu/drm/i915/i915_query.c
> > > @@ -10,6 +10,7 @@
> > >   #include "i915_perf.h"
> > >   #include "i915_query.h"
> > >   #include <uapi/drm/i915_drm.h>
> > > +#include "gt/intel_gt.h"
> > > 
> > >   static int copy_query_item(void *query_hdr, size_t query_sz,
> > >                             u32 total_length,
> > > @@ -502,6 +503,26 @@ static int query_hwconfig_table(struct drm_i915_private *i915,
> > >          return hwconfig->size;
> > >   }
> > > 
> > > +static int query_l3banks(struct drm_i915_private *i915,
> > > +                        struct drm_i915_query_item *query_item)
> > > +{
> > > +       u32 banks;
> > > +
> > > +       if (query_item->length == 0)
> > > +               return sizeof(banks);
> > > +
> > > +       if (query_item->length < sizeof(banks))
> > > +               return -EINVAL;
> > > +
> > > +       banks = intel_gt_get_l3bank_count(&i915->gt);
> > > +
> > > +       if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
> > > +                        &banks, sizeof(banks)))
> > > +               return -EFAULT;
> > > +
> > > +       return sizeof(banks);
> > > +}
> > > +
> > >   static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
> > >                                          struct drm_i915_query_item *query_item) = {
> > >          query_topology_info,
> > > @@ -509,6 +530,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
> > >          query_perf_config,
> > >          query_memregion_info,
> > >          query_hwconfig_table,
> > > +       query_l3banks,
> > >   };
> > > 
> > >   int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index eb13c601d680..e9ba88fe3db7 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -3099,6 +3099,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> > >   #define        GEN10_MIRROR_FUSE3              _MMIO(0x9118)
> > >   #define GEN10_L3BANK_PAIR_COUNT     4
> > >   #define GEN10_L3BANK_MASK   0x0F
> > > +#define GEN12_GT_L3_MODE_MASK 0xFF
> > > 
> > >   #define GEN8_EU_DISABLE0               _MMIO(0x9134)
> > >   #define   GEN8_EU_DIS0_S0_MASK         0xffffff
> > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > > index 87d369cae22a..20d18cca5066 100644
> > > --- a/include/uapi/drm/i915_drm.h
> > > +++ b/include/uapi/drm/i915_drm.h
> > > @@ -2234,6 +2234,7 @@ struct drm_i915_query_item {
> > >   #define DRM_I915_QUERY_PERF_CONFIG      3
> > >   #define DRM_I915_QUERY_MEMORY_REGIONS   4
> > >   #define DRM_I915_QUERY_HWCONFIG_TABLE   5
> > > +#define DRM_I915_QUERY_L3_BANK_COUNT    6
> > >   /* Must be kept compact -- no holes and well documented */
> > > 
> > >          /**
> > > --
> > > 2.25.1
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > 
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 2161bf01ef8b..708bb3581d83 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -704,3 +704,18 @@  void intel_gt_info_print(const struct intel_gt_info *info,
 
 	intel_sseu_dump(&info->sseu, p);
 }
+
+int intel_gt_get_l3bank_count(struct intel_gt *gt)
+{
+	struct drm_i915_private *i915 = gt->i915;
+	intel_wakeref_t wakeref;
+	u32 fuse3;
+
+	if (GRAPHICS_VER(i915) < 12)
+		return -ENODEV;
+
+	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+		fuse3 = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
+
+	return hweight32(REG_FIELD_GET(GEN12_GT_L3_MODE_MASK, ~fuse3));
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 7ec395cace69..46aa1cf4cf30 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -77,6 +77,7 @@  static inline bool intel_gt_is_wedged(const struct intel_gt *gt)
 
 void intel_gt_info_print(const struct intel_gt_info *info,
 			 struct drm_printer *p);
+int intel_gt_get_l3bank_count(struct intel_gt *gt);
 
 void intel_gt_watchdog_work(struct work_struct *work);
 
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 96bd8fb3e895..0e92bb2d21b2 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -10,6 +10,7 @@ 
 #include "i915_perf.h"
 #include "i915_query.h"
 #include <uapi/drm/i915_drm.h>
+#include "gt/intel_gt.h"
 
 static int copy_query_item(void *query_hdr, size_t query_sz,
 			   u32 total_length,
@@ -502,6 +503,26 @@  static int query_hwconfig_table(struct drm_i915_private *i915,
 	return hwconfig->size;
 }
 
+static int query_l3banks(struct drm_i915_private *i915,
+			 struct drm_i915_query_item *query_item)
+{
+	u32 banks;
+
+	if (query_item->length == 0)
+		return sizeof(banks);
+
+	if (query_item->length < sizeof(banks))
+		return -EINVAL;
+
+	banks = intel_gt_get_l3bank_count(&i915->gt);
+
+	if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
+			 &banks, sizeof(banks)))
+		return -EFAULT;
+
+	return sizeof(banks);
+}
+
 static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
 					struct drm_i915_query_item *query_item) = {
 	query_topology_info,
@@ -509,6 +530,7 @@  static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
 	query_perf_config,
 	query_memregion_info,
 	query_hwconfig_table,
+	query_l3banks,
 };
 
 int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eb13c601d680..e9ba88fe3db7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3099,6 +3099,7 @@  static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
 #define GEN10_L3BANK_PAIR_COUNT     4
 #define GEN10_L3BANK_MASK   0x0F
+#define GEN12_GT_L3_MODE_MASK 0xFF
 
 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 87d369cae22a..20d18cca5066 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2234,6 +2234,7 @@  struct drm_i915_query_item {
 #define DRM_I915_QUERY_PERF_CONFIG      3
 #define DRM_I915_QUERY_MEMORY_REGIONS   4
 #define DRM_I915_QUERY_HWCONFIG_TABLE   5
+#define DRM_I915_QUERY_L3_BANK_COUNT    6
 /* Must be kept compact -- no holes and well documented */
 
 	/**