@@ -88,6 +88,7 @@ extern struct omap_volt_data omap34xx_vddmpu_volt_data[];
extern struct omap_volt_data omap34xx_vddcore_volt_data[];
extern struct omap_volt_data omap36xx_vddmpu_volt_data[];
extern struct omap_volt_data omap36xx_vddcore_volt_data[];
+extern struct omap_volt_data am35xx_vdd_volt_data[];
extern struct omap_volt_data omap44xx_vdd_mpu_volt_data[];
extern struct omap_volt_data omap44xx_vdd_iva_volt_data[];
@@ -150,6 +150,16 @@ static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
OPP_INITIALIZER("iva", false, 800000000, OMAP3630_VDD_MPU_OPP1G_UV),
};
+/* AM35x
+ *
+ * Fields related to SmartReflex and Voltage Processor are set to 0.
+ */
+struct omap_volt_data am35xx_vdd_volt_data[] = {
+ VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, 0x0, 0x0, 0x0),
+ VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+
+
/**
* omap3_opp_init() - initialize omap3 opp table
*/
@@ -227,7 +227,8 @@ static void __init omap3_init_voltages(void)
{
if (!cpu_is_omap34xx())
return;
-
+ if (cpu_is_omap3505() || cpu_is_omap3517())
+ return;
omap2_set_init_voltage("mpu", "dpll1_ck", mpu_dev);
omap2_set_init_voltage("core", "l3_ick", l3_dev);
}
@@ -60,6 +60,12 @@ static struct dentry *voltage_dir;
static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
unsigned long target_volt);
+static int volt_scale_nop(struct omap_vdd_info *vdd,
+ unsigned long target_volt)
+{
+ return 0;
+}
+
static u32 omap3_voltage_read_reg(u16 mod, u8 offset)
{
return omap2_prm_read_mod_reg(mod, offset);
@@ -114,6 +120,12 @@ static int __init _config_common_vdd_data(struct omap_vdd_info *vdd)
sys_clk_speed /= 1000;
/* Generic voltage parameters */
+ if (cpu_is_omap3505() || cpu_is_omap3517()) {
+ vdd->volt_scale = volt_scale_nop;
+ vdd->vp_enabled = false;
+ return 0;
+ }
+
vdd->volt_scale = vp_forceupdate_scale_voltage;
vdd->vp_enabled = false;
@@ -217,6 +229,9 @@ static void __init vp_init(struct omap_vdd_info *vdd)
{
u32 vp_val;
+ if (cpu_is_omap3505() || cpu_is_omap3517())
+ return ;
+
if (!vdd->read_reg || !vdd->write_reg) {
pr_err("%s: No read/write API for accessing vdd_%s regs\n",
__func__, vdd->voltdm.name);
@@ -598,6 +613,9 @@ static void __init omap_vc_init(struct omap_vdd_info *vdd)
{
u32 vc_val;
+ if (cpu_is_omap3505() || cpu_is_omap3517())
+ return ;
+
if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
pr_err("%s: PMIC info requried to configure vc for"
"vdd_%s not populated.Hence cannot initialize vc\n",
@@ -67,6 +67,38 @@ static struct omap_vdd_info *omap3_vdd_info[] = {
&omap3_vdd2_info,
};
+/*
+ * AM35x VDD structures
+ *
+ * In AM35x there neither scalable voltage domain nor any hook-up with
+ * voltage controller/processor. However, when trying to re-use the hwmod
+ * database for OMAP3, definition of "core" voltage domain is necessary.
+ * Else, changes in hwmod data structures grow spirally.
+ *
+ * As a workaround, "core" voltage domain is defined below. The definition
+ * doesn't lead to any side-effects.
+ */
+static struct omap_vdd_info am3517_vdd1_info = {
+ .vp_enabled = false,
+
+ .voltdm = {
+ .name = "mpu",
+ },
+};
+
+static struct omap_vdd_info am3517_vdd2_info = {
+ .vp_enabled = false,
+
+ .voltdm = {
+ .name = "core",
+ },
+};
+
+static struct omap_vdd_info *am3517_vdd_info[] = {
+ &am3517_vdd1_info,
+ &am3517_vdd2_info,
+};
+
/* OMAP3 specific voltage init functions */
static int __init omap3xxx_voltage_early_init(void)
{
@@ -80,7 +112,13 @@ static int __init omap3xxx_voltage_early_init(void)
* XXX Will depend on the process, validation, and binning
* for the currently-running IC
*/
- if (cpu_is_omap3630()) {
+ if (cpu_is_omap3505() || cpu_is_omap3517()) {
+ am3517_vdd1_info.volt_data = am35xx_vdd_volt_data;
+ am3517_vdd2_info.volt_data = am35xx_vdd_volt_data;
+ return omap_voltage_early_init(prm_mod, prm_irqst_ocp_mod,
+ am3517_vdd_info,
+ ARRAY_SIZE(am3517_vdd_info));
+ } else if (cpu_is_omap3630()) {
omap3_vdd1_info.volt_data = omap36xx_vddmpu_volt_data;
omap3_vdd2_info.volt_data = omap36xx_vddcore_volt_data;
} else {