| Message ID | 20210621165230.6.Icde6be7601a5939960caf802056c88cd5132eb4e@changeid (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
| Series | iommu: Enable devices to request non-strict DMA, starting with QCom SD/MMC | expand |
On Mon, Jun 21, 2021 at 04:52:48PM -0700, Douglas Anderson wrote: > IOMMUs can be run in "strict" mode or in "non-strict" mode. The > quick-summary difference between the two is that in "strict" mode we > wait until everything is flushed out when we unmap DMA memory. In > "non-strict" we don't. > > Using the IOMMU in "strict" mode is more secure/safer but slower > because we have to sit and wait for flushes while we're unmapping. To > explain a bit why "non-strict" mode is unsafe, let's imagine two > examples. > > An example of "non-strict" being insecure when reading from a device: > a) Linux driver maps memory for DMA. > b) Linux driver starts DMA on the device. > c) Device write to RAM subject to bounds checking done by IOMMU. > d) Device finishes writing to RAM and signals transfer is finished. > e) Linux driver starts unmapping DMA memory but doesn't flush. Why doesn't it "flush"? > f) Linux driver validates that the data in memory looks sane and that > accessing it won't cause the driver to, for instance, overflow a > buffer. > g) Device takes advantage of knowledge of how the Linux driver works > and sneaks in a modification to the data after the validation but > before the IOMMU unmap flush finishes. > h) Device has now caused the Linux driver to access memory it > shouldn't. So you are now saying we need to not trust hardware? If so, that's a massive switch for how the kernel needs to work right? And what driver does f) and allows g) to happen? That would be a normal bug anyway, why not just fix the driver? > An example of "non-strict" being insecure when writing to a device: > a) Linux driver writes data intended for the device to RAM. > b) Linux driver maps memory for DMA. > c) Linux driver starts DMA on the device. > d) Device reads from RAM subject to bounds checking done by IOMMU. > e) Device finishes reading from RAM and signals transfer is finished. > f) Linux driver starts unmapping DMA memory but doesn't flush. Why does it not flush? What do you mean by "flush" > g) Linux driver frees memory and returns it to the pool. What pool? > h) Memory is allocated for another purpose. Allocated by what? We have memory allocators that write over the data when freed, why not just use this if you are concerned about this type of issue? > i) Device takes advantage of the period of time before IOMMU flush to > read memory that it shouldn't have had access to. What memory would that be? And if you really care about these issues, are you not able to take the "hit" for the flush all the time as that is a hardware thing, not a software thing. Why not just always take advantage of that, no driver changes needed? And this isn't going to work, again, because the "pre_probe" isn't going to be acceptable, sorry. greg k-h
Hi, On Thu, Jun 24, 2021 at 6:43 AM Greg KH <gregkh@linuxfoundation.org> wrote: > > On Mon, Jun 21, 2021 at 04:52:48PM -0700, Douglas Anderson wrote: > > IOMMUs can be run in "strict" mode or in "non-strict" mode. The > > quick-summary difference between the two is that in "strict" mode we > > wait until everything is flushed out when we unmap DMA memory. In > > "non-strict" we don't. > > > > Using the IOMMU in "strict" mode is more secure/safer but slower > > because we have to sit and wait for flushes while we're unmapping. To > > explain a bit why "non-strict" mode is unsafe, let's imagine two > > examples. > > > > An example of "non-strict" being insecure when reading from a device: > > a) Linux driver maps memory for DMA. > > b) Linux driver starts DMA on the device. > > c) Device write to RAM subject to bounds checking done by IOMMU. > > d) Device finishes writing to RAM and signals transfer is finished. > > e) Linux driver starts unmapping DMA memory but doesn't flush. > > Why doesn't it "flush"? This is just how the pre-existing "iommu.strict=0" command line parameter works. > > f) Linux driver validates that the data in memory looks sane and that > > accessing it won't cause the driver to, for instance, overflow a > > buffer. > > g) Device takes advantage of knowledge of how the Linux driver works > > and sneaks in a modification to the data after the validation but > > before the IOMMU unmap flush finishes. > > h) Device has now caused the Linux driver to access memory it > > shouldn't. > > So you are now saying we need to not trust hardware? If so, that's a > massive switch for how the kernel needs to work right? This is a pre-existing concept in the kernel and is in fact so prevalent that there are a bunch of inconsistent ways to configure it (though it's being made better [1]) * On ARM64, default is strict and you can configure it with iommu.strict * On AMD, default is non-strict and you can configure it with amd_iommu=fullflush * On Intel, default is non-strict and you can configure it with intel_iommu=strict ...also pre-existing is that the kernel has special cases for "external" PCI devices where it forces them to strict mode even if the default is non-strict (like on Intel and AMD). I was pointed specifically at <http://thunderclap.io/> for an example of why this was important. > And what driver does f) and allows g) to happen? That would be a normal > bug anyway, why not just fix the driver? This one would be possible to workaround in the driver by copying the memory somewhere else, but it violates the DMA model. Specifically step "e)" above is supposed to mean that the driver is now in full control of the memory, so it should be perfectly justified in assuming that nobody else is scribbling on it. > > An example of "non-strict" being insecure when writing to a device: > > a) Linux driver writes data intended for the device to RAM. > > b) Linux driver maps memory for DMA. > > c) Linux driver starts DMA on the device. > > d) Device reads from RAM subject to bounds checking done by IOMMU. > > e) Device finishes reading from RAM and signals transfer is finished. > > f) Linux driver starts unmapping DMA memory but doesn't flush. > > Why does it not flush? > > What do you mean by "flush" "flush" means force / wait for the IOMMU unmap to fully take effect. > > g) Linux driver frees memory and returns it to the pool. > > What pool? The normal Linux memory pool. > > h) Memory is allocated for another purpose. > > Allocated by what? Someone else that wanted memory. > We have memory allocators that write over the data when freed, why not > just use this if you are concerned about this type of issue? > > > i) Device takes advantage of the period of time before IOMMU flush to > > read memory that it shouldn't have had access to. > > What memory would that be? Depends on who got it. This could be hard to predict unless a peripheral was trying to exploit a very specific version of Linux where maybe it was predictable who got the memory next. > And if you really care about these issues, are you not able to take the > "hit" for the flush all the time as that is a hardware thing, not a > software thing. Why not just always take advantage of that, no driver > changes needed? The whole concept of strict vs. non-strict is definitely not new to my series and I'm mostly just trying to configure it properly. > And this isn't going to work, again, because the "pre_probe" isn't going > to be acceptable, sorry. Right. As discussed in the cover letter, I'm going to try to solve this in other ways that doesn't involve pre_probe. [1] https://lore.kernel.org/linux-iommu/1624016058-189713-1-git-send-email-john.garry@huawei.com/T/#m21bc07b9353b3ba85f2a40557645c2bcc13cbb3e -Doug
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index e44b7a66b73c..33ef5e6941d7 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -2465,6 +2465,13 @@ static inline void sdhci_msm_get_of_property(struct platform_device *pdev, } +static int sdhci_msm_pre_probe(struct device *dev) +{ + dev->request_non_strict_iommu = true; + + return 0; +} + static int sdhci_msm_probe(struct platform_device *pdev) { struct sdhci_host *host; @@ -2811,6 +2818,7 @@ static struct platform_driver sdhci_msm_driver = { .of_match_table = sdhci_msm_dt_match, .pm = &sdhci_msm_pm_ops, .probe_type = PROBE_PREFER_ASYNCHRONOUS, + .pre_probe = sdhci_msm_pre_probe, }, };
IOMMUs can be run in "strict" mode or in "non-strict" mode. The quick-summary difference between the two is that in "strict" mode we wait until everything is flushed out when we unmap DMA memory. In "non-strict" we don't. Using the IOMMU in "strict" mode is more secure/safer but slower because we have to sit and wait for flushes while we're unmapping. To explain a bit why "non-strict" mode is unsafe, let's imagine two examples. An example of "non-strict" being insecure when reading from a device: a) Linux driver maps memory for DMA. b) Linux driver starts DMA on the device. c) Device write to RAM subject to bounds checking done by IOMMU. d) Device finishes writing to RAM and signals transfer is finished. e) Linux driver starts unmapping DMA memory but doesn't flush. f) Linux driver validates that the data in memory looks sane and that accessing it won't cause the driver to, for instance, overflow a buffer. g) Device takes advantage of knowledge of how the Linux driver works and sneaks in a modification to the data after the validation but before the IOMMU unmap flush finishes. h) Device has now caused the Linux driver to access memory it shouldn't. An example of "non-strict" being insecure when writing to a device: a) Linux driver writes data intended for the device to RAM. b) Linux driver maps memory for DMA. c) Linux driver starts DMA on the device. d) Device reads from RAM subject to bounds checking done by IOMMU. e) Device finishes reading from RAM and signals transfer is finished. f) Linux driver starts unmapping DMA memory but doesn't flush. g) Linux driver frees memory and returns it to the pool. h) Memory is allocated for another purpose. i) Device takes advantage of the period of time before IOMMU flush to read memory that it shouldn't have had access to. As you can see from the above examples, using the iommu in "non-strict" mode might not sound _too_ scary (the window of badness is small and the exposed memory is small) but there is certainly risk. Let's evaluate the risk by breaking it down into two problems that IOMMUs are supposed to be protecting us against: Case 1: IOMMUs prevent malicious code running on the peripheral (maybe a malicious peripheral or maybe someone exploited a benign peripheral) from turning into an exploit of the Linux kernel. This is particularly important if the peripheral has loadable / updatable firmware or if the peripheral has some type of general purpose processor and is processing untrusted inputs. It's also important if the device is something that can be easily plugged into the host and the device has direct DMA access itself, like a PCIe device. Case 2: IOMMUs limit the severity of a class of software bugs in the kernel. If we misconfigure a peripheral by accident then instead of the peripheral clobbering random memory due to a bug we might get an IOMMU error. Now that we understand the issue and the risks, let's evaluate whether we really need "strict" mode for the Qualcomm SDHCI controllers. I will make the argument that we don't _need_ strict mode for them. Why? * The SDHCI controller on Qualcomm SoCs doesn't appear to have loadable / updatable firmware and, assuming it's got some firmware baked into it, I see no evidence that the firmware could be compromised. * Even though, for external SD cards in particular, the controller is dealing with "untrusted" inputs, it's dealing with them in a very controlled way. It seems unlikely that a rogue SD card would be able to present something to the SDHCI controller that would cause it to DMA to/from an address other than one the kernel told it about. * Although it would be nice to catch more software bugs, once the Linux driver has been debugged and stressed the value is not very high. If the IOMMU caught something like this the system would be in a pretty bad shape anyway (we don't really recover from IOMMU errors) and the only benefit would be a better spotlight on what went wrong. Now we have a good understanding of the benefits of "strict" mode for our SDHCI controllers, let's look at some performance numbers. I used "dd" to measure read speeds from eMMC on a sc7180-trogdor-lazor board. Basic test command (while booted from USB): echo 3 > /proc/sys/vm/drop_caches dd if=/dev/mmcblk1 of=/dev/null bs=4M count=512 I attempted to run my tests for enough iterations that results stabilized and weren't too noisy. Tests were run with patches picked to the chromeos-5.4 tree (sanity checked against v5.13-rc7). I also attempted to compare to other attempts to address IOMMU problems and/or attempts to bump the cpufreq up to solve this problem: - eMMC datasheet spec: 300 MB/s "Typical Sequential Performance" NOTE: we're driving the bus at 192 MHz instead of 200 Mhz so we might not be able to achieve the full 300 MB/s. - Baseline: 210.9 MB/s - Baseline + peg cpufreq to max: 284.3 MB/s - This patch: 279.6 MB/s - This patch + peg cpufreq to max: 288.1 MB/s - Joel's IO Wait fix [1]: 258.4 MB/s - Joel's IO Wait fix [1] + peg cpufreq to max: 287.8 MB/s - TLBIVA patches [2] + [3]: 214.7 MB/s - TLBIVA patches [2] + [3] + peg cpufreq to max: 285.7 MB/s - This patch plus Joel's [1]: 280.2 MB/s - This patch plus Joel's [1] + peg...: 279.0 MB/s NOTE: I suspect something in the system was thermal throttling since there's a heat wave right now. I also spent a little bit of time trying to see if I could get the IOMMU flush for MMC out of the critical path but was unable to figure out how to do this and get good performance. Overall I'd say that the performance results above show: * It's really not straightforward to point at "one thing" that is making our eMMC performance bad. * It's certainly possible to get pretty good eMMC performance even without this patch. * This patch makes it much easier to get good eMMC performance. * No other solutions that I found resulted in quite as good eMMC performance as having this patch. Given all the above (security safety concerns are minimal and it's a nice performance win), I'm proposing that running SDHCI on Qualcomm SoCs in non-strict mode is the right thing to do until such point in time as someone can come up with a better solution to get good SD/eMMC performance without it. NOTES: * It's likely that arguments similar to the above can be made for other SDHCI controllers. However, given that this is something that can have an impact on security it feels like we want each SDHCI controller to opt-in. I believe it is conceivable, for instance, that some SDHCI controllers might have loadable or updatable firmware. * It's also likely other peripherals will want this to get the quick performance win. That also should be fine, though anyone landing a similar patch should be very careful that it is low risk for all users of a given peripheral. * Conceivably if even this patch is considered too "high risk", we could limit this to just non-removable cards (like eMMC) by just checking the device tree. This is one nice advantage of using the pre_probe() to set this. [1] https://lore.kernel.org/r/20210618040639.3113489-1-joel@joelfernandes.org [2] https://lore.kernel.org/r/1623850736-389584-1-git-send-email-quic_c_gdjako@quicinc.com/ [3] https://lore.kernel.org/r/cover.1623981933.git.saiprakash.ranjan@codeaurora.org/ Signed-off-by: Douglas Anderson <dianders@chromium.org> --- drivers/mmc/host/sdhci-msm.c | 8 ++++++++ 1 file changed, 8 insertions(+)