| Message ID | 1624688321-69131-6-git-send-email-zhouyanjie@wanyeetech.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 34c522a07ccbfb0e6476713b41a09f9f51a06c9f |
| Headers | show |
| Series | Misc Ingenic patches. | expand |
Hi Zhou, Le sam., juin 26 2021 at 14:18:41 +0800, 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> a écrit : > 1.Add a new TCU channel as the percpu timer of core1, this is to > prepare for the subsequent SMP support. The newly added channel > will not adversely affect the current single-core state. > 2.Adjust the position of TCU node to make it consistent with the > order in jz4780.dtsi file. > > Tested-by: Nikolaus Schaller <hns@goldelico.com> # on CI20 > Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Again, you should avoid moving nodes like that. Not sure it's worth asking for a v5, so: Acked-by: Paul Cercueil <paul@crapouillou.net> Cheers, -Paul > --- > > Notes: > v2: > New patch. > > v2->v3: > No change. > > v3->v4: > Improve TCU related notes. > > arch/mips/boot/dts/ingenic/ci20.dts | 24 ++++++++++++++---------- > 1 file changed, 14 insertions(+), 10 deletions(-) > > diff --git a/arch/mips/boot/dts/ingenic/ci20.dts > b/arch/mips/boot/dts/ingenic/ci20.dts > index 3a4eaf1..61c153b 100644 > --- a/arch/mips/boot/dts/ingenic/ci20.dts > +++ b/arch/mips/boot/dts/ingenic/ci20.dts > @@ -118,6 +118,20 @@ > assigned-clock-rates = <48000000>; > }; > > +&tcu { > + /* > + * 750 kHz for the system timers and clocksource, > + * use channel #0 and #1 for the per cpu system timers, > + * and use channel #2 for the clocksource. > + * > + * 3000 kHz for the OST timer to provide a higher > + * precision clocksource. > + */ > + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, > + <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>; > + assigned-clock-rates = <750000>, <750000>, <750000>, <3000000>; > +}; > + > &mmc0 { > status = "okay"; > > @@ -522,13 +536,3 @@ > bias-disable; > }; > }; > - > -&tcu { > - /* > - * 750 kHz for the system timer and clocksource, > - * use channel #0 for the system timer, #1 for the clocksource. > - */ > - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, > - <&tcu TCU_CLK_OST>; > - assigned-clock-rates = <750000>, <750000>, <3000000>; > -}; > -- > 2.7.4 >
On 2021/6/30 下午8:24, Paul Cercueil wrote: > Hi Zhou, > > Le sam., juin 26 2021 at 14:18:41 +0800, 周琰杰 (Zhou Yanjie) > <zhouyanjie@wanyeetech.com> a écrit : >> 1.Add a new TCU channel as the percpu timer of core1, this is to >> prepare for the subsequent SMP support. The newly added channel >> will not adversely affect the current single-core state. >> 2.Adjust the position of TCU node to make it consistent with the >> order in jz4780.dtsi file. >> >> Tested-by: Nikolaus Schaller <hns@goldelico.com> # on CI20 >> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> > > Again, you should avoid moving nodes like that. Oops, sorry, forgot to fix it, I will be more careful next time. > > Not sure it's worth asking for a v5, so: > Acked-by: Paul Cercueil <paul@crapouillou.net> > Thanks! > Cheers, > -Paul > >> --- >> >> Notes: >> v2: >> New patch. >> >> v2->v3: >> No change. >> >> v3->v4: >> Improve TCU related notes. >> >> arch/mips/boot/dts/ingenic/ci20.dts | 24 ++++++++++++++---------- >> 1 file changed, 14 insertions(+), 10 deletions(-) >> >> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts >> b/arch/mips/boot/dts/ingenic/ci20.dts >> index 3a4eaf1..61c153b 100644 >> --- a/arch/mips/boot/dts/ingenic/ci20.dts >> +++ b/arch/mips/boot/dts/ingenic/ci20.dts >> @@ -118,6 +118,20 @@ >> assigned-clock-rates = <48000000>; >> }; >> >> +&tcu { >> + /* >> + * 750 kHz for the system timers and clocksource, >> + * use channel #0 and #1 for the per cpu system timers, >> + * and use channel #2 for the clocksource. >> + * >> + * 3000 kHz for the OST timer to provide a higher >> + * precision clocksource. >> + */ >> + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, >> + <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>; >> + assigned-clock-rates = <750000>, <750000>, <750000>, <3000000>; >> +}; >> + >> &mmc0 { >> status = "okay"; >> >> @@ -522,13 +536,3 @@ >> bias-disable; >> }; >> }; >> - >> -&tcu { >> - /* >> - * 750 kHz for the system timer and clocksource, >> - * use channel #0 for the system timer, #1 for the clocksource. >> - */ >> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, >> - <&tcu TCU_CLK_OST>; >> - assigned-clock-rates = <750000>, <750000>, <3000000>; >> -}; >> -- >> 2.7.4 >> >
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 3a4eaf1..61c153b 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -118,6 +118,20 @@ assigned-clock-rates = <48000000>; }; +&tcu { + /* + * 750 kHz for the system timers and clocksource, + * use channel #0 and #1 for the per cpu system timers, + * and use channel #2 for the clocksource. + * + * 3000 kHz for the OST timer to provide a higher + * precision clocksource. + */ + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, + <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>; + assigned-clock-rates = <750000>, <750000>, <750000>, <3000000>; +}; + &mmc0 { status = "okay"; @@ -522,13 +536,3 @@ bias-disable; }; }; - -&tcu { - /* - * 750 kHz for the system timer and clocksource, - * use channel #0 for the system timer, #1 for the clocksource. - */ - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, - <&tcu TCU_CLK_OST>; - assigned-clock-rates = <750000>, <750000>, <3000000>; -};