mbox series

[v10,0/5] arm64: mte: allow async MTE to be upgraded to sync on a per-CPU basis

Message ID 20210713234801.3858018-1-pcc@google.com (mailing list archive)
Headers show
Series arm64: mte: allow async MTE to be upgraded to sync on a per-CPU basis | expand

Message

Peter Collingbourne July 13, 2021, 11:47 p.m. UTC
On some CPUs the performance of MTE in synchronous mode is similar
to that of asynchronous mode. This makes it worthwhile to enable
synchronous mode on those CPUs when asynchronous mode is requested,
in order to gain the error detection benefits of synchronous mode
without the performance downsides. Therefore, make it possible for
user programs to opt into upgrading to synchronous mode on those CPUs.

This is done by introducing a notion of a preferred TCF mode, which is
controlled on a per-CPU basis by a sysfs node. The existing SYNC and
ASYNC TCF settings are repurposed as bitfields that specify a set of
possible modes. If the preferred TCF mode for a particular CPU is in
the user-provided mode set (this will always be the case for mode sets
containing more than one mode because the kernel only supports two tag
checking modes, but future kernels may support more modes) then that
mode is used when running on that CPU, otherwise one of the modes in
the task's mode set will be selected in a currently unspecified manner.

v8:
- split into multiple patches
- remove MTE_CTRL_TCF_NONE
- improve documentation
- disable preemption and add comment to mte_update_sctlr_user
- bring back PR_MTE_TCF_SHIFT for source compatibility
- address formatting nit

v7:
- switch to new API proposed on list

v6:
- switch to strings in sysfs nodes instead of TCF values

v5:
- updated documentation
- address some nits in mte.c

v4:
- switch to new mte_ctrl field
- make register_mte_upgrade_async_sysctl return an int
- change the sysctl to take 0 or 1 instead of raw TCF values
- "same as" -> "similar to"

v3:
- drop the device tree support
- add documentation
- add static_assert to ensure no overlap with real HW bits
- move per-CPU variable initialization to mte.c
- use smp_call_function_single instead of stop_machine

v2:
- make it an opt-in behavior
- change the format of the device tree node
- also allow controlling the feature via sysfs

Peter Collingbourne (5):
  arm64: mte: rename gcr_user_excl to mte_ctrl
  arm64: mte: change ASYNC and SYNC TCF settings into bitfields
  arm64: move preemption disablement to prctl handlers
  arm64: mte: introduce a per-CPU tag checking mode preference
  Documentation: document the preferred tag checking mode feature

 .../ABI/testing/sysfs-devices-system-cpu      |  18 +++
 .../arm64/memory-tagging-extension.rst        |  48 +++++-
 arch/arm64/include/asm/pointer_auth.h         |  12 +-
 arch/arm64/include/asm/processor.h            |  10 +-
 arch/arm64/kernel/asm-offsets.c               |   2 +-
 arch/arm64/kernel/entry.S                     |   4 +-
 arch/arm64/kernel/mte.c                       | 139 ++++++++++++------
 arch/arm64/kernel/pointer_auth.c              |  10 +-
 arch/arm64/kernel/process.c                   |  21 +--
 include/uapi/linux/prctl.h                    |  11 +-
 10 files changed, 189 insertions(+), 86 deletions(-)

Comments

Catalin Marinas July 27, 2021, 6:20 p.m. UTC | #1
Hi Peter,

On Tue, Jul 13, 2021 at 04:47:56PM -0700, Peter Collingbourne wrote:
> Peter Collingbourne (5):
>   arm64: mte: rename gcr_user_excl to mte_ctrl
>   arm64: mte: change ASYNC and SYNC TCF settings into bitfields
>   arm64: move preemption disablement to prctl handlers
>   arm64: mte: introduce a per-CPU tag checking mode preference
>   Documentation: document the preferred tag checking mode feature

Could you please rebase these patches on top of arm64 for-next/mte
(based on 5.14-rc3)? They don't apply cleanly. You may want to update
the other GCR_EL1 and double ISB patches as well in case there's a
specific order in which they need to be applied.

Thanks.
Peter Collingbourne July 27, 2021, 8:54 p.m. UTC | #2
On Tue, Jul 27, 2021 at 11:20 AM Catalin Marinas
<catalin.marinas@arm.com> wrote:
>
> Hi Peter,
>
> On Tue, Jul 13, 2021 at 04:47:56PM -0700, Peter Collingbourne wrote:
> > Peter Collingbourne (5):
> >   arm64: mte: rename gcr_user_excl to mte_ctrl
> >   arm64: mte: change ASYNC and SYNC TCF settings into bitfields
> >   arm64: move preemption disablement to prctl handlers
> >   arm64: mte: introduce a per-CPU tag checking mode preference
> >   Documentation: document the preferred tag checking mode feature
>
> Could you please rebase these patches on top of arm64 for-next/mte
> (based on 5.14-rc3)? They don't apply cleanly. You may want to update
> the other GCR_EL1 and double ISB patches as well in case there's a
> specific order in which they need to be applied.

Okay, I rebased this series and the double ISB patch to 5.14-rc3 (the
GCR_EL1 patch didn't need to be rebased). I also double checked that
there aren't any conflicts with the TFSR patch that you've already
taken. The GCR_EL1 patch needs to be applied after this series, and
the double ISB patch doesn't need to be applied in any particular
order.


Peter