| Message ID | 20210728135534.703028-6-pgwipeout@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | fixes and enablement for rk356x | expand |
Am Mittwoch, 28. Juli 2021, 15:55:30 CEST schrieb Peter Geis: > Add the thermal and tsadc nodes to the rk3568 device tree. > There are two sensors, one for the cpu, one for the gpu. > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > --- > .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 6 ++ > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 71 +++++++++++++++++++ > 2 files changed, 77 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > index a588ca95ace2..b464c7bda1f7 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > @@ -2420,6 +2420,12 @@ spi3m1_cs1: spi3m1-cs1 { > }; > > tsadc { > + /omit-if-no-ref/ > + tsadc_gpio: tsadc-gpio { > + rockchip,pins = > + <0 RK_PA1 0 &pcfg_pull_none>; > + }; > + > /omit-if-no-ref/ > tsadcm0_shut: tsadcm0-shut { > rockchip,pins = > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > index 77c679304916..0905fac0726a 100644 > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > @@ -51,6 +51,7 @@ cpu0: cpu@0 { > compatible = "arm,cortex-a55"; > reg = <0x0 0x0>; > clocks = <&scmi_clk 0>; > + #cooling-cells = <2>; > enable-method = "psci"; > operating-points-v2 = <&cpu0_opp_table>; > }; > @@ -59,6 +60,7 @@ cpu1: cpu@100 { > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x100>; > + #cooling-cells = <2>; > enable-method = "psci"; > operating-points-v2 = <&cpu0_opp_table>; > }; > @@ -67,6 +69,7 @@ cpu2: cpu@200 { > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x200>; > + #cooling-cells = <2>; > enable-method = "psci"; > operating-points-v2 = <&cpu0_opp_table>; > }; > @@ -75,6 +78,7 @@ cpu3: cpu@300 { > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x300>; > + #cooling-cells = <2>; > enable-method = "psci"; > operating-points-v2 = <&cpu0_opp_table>; > }; > @@ -774,6 +778,73 @@ uart9: serial@fe6d0000 { > status = "disabled"; > }; > > + thermal_zones: thermal-zones { > + cpu_thermal: cpu-thermal { > + polling-delay-passive = <100>; > + polling-delay = <1000>; > + > + thermal-sensors = <&tsadc 0>; > + > + trips { > + cpu_alert0: cpu_alert0 { > + temperature = <70000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + cpu_alert1: cpu_alert1 { > + temperature = <75000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + cpu_crit: cpu_crit { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "critical"; > + }; > + }; > + > + cooling-maps { > + map0 { > + trip = <&cpu_alert0>; > + cooling-device = > + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + }; > + > + gpu_thermal: gpu-thermal { > + polling-delay-passive = <20>; /* milliseconds */ > + polling-delay = <1000>; /* milliseconds */ > + > + thermal-sensors = <&tsadc 1>; > + }; > + }; > + > + tsadc: tsadc@fe710000 { > + compatible = "rockchip,rk3568-tsadc"; > + reg = <0x0 0xfe710000 0x0 0x100>; > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; > + assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; > + assigned-clock-rates = <17000000>, <700000>; > + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; > + clock-names = "tsadc", "apb_pclk"; > + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, > + <&cru SRST_TSADCPHY>; > + reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; > + rockchip,grf = <&grf>; > + rockchip,hw-tshut-temp = <95000>; > + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ > + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ > + pinctrl-names = "gpio", "otpout"; > + pinctrl-0 = <&tsadc_gpio>; > + pinctrl-1 = <&tsadc_shutorg>; The mainline thermal driver doesn't specify these pinctrl states at all. Heiko > + #thermal-sensor-cells = <1>; > + status = "disabled"; > + }; > + > saradc: saradc@fe720000 { > compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; > reg = <0x0 0xfe720000 0x0 0x100>; >
On Wed, Jul 28, 2021 at 10:46 AM Heiko Stübner <heiko@sntech.de> wrote: > > Am Mittwoch, 28. Juli 2021, 15:55:30 CEST schrieb Peter Geis: > > Add the thermal and tsadc nodes to the rk3568 device tree. > > There are two sensors, one for the cpu, one for the gpu. > > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > > --- > > .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 6 ++ > > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 71 +++++++++++++++++++ > > 2 files changed, 77 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > > index a588ca95ace2..b464c7bda1f7 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > > +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > > @@ -2420,6 +2420,12 @@ spi3m1_cs1: spi3m1-cs1 { > > }; > > > > tsadc { > > + /omit-if-no-ref/ > > + tsadc_gpio: tsadc-gpio { > > + rockchip,pins = > > + <0 RK_PA1 0 &pcfg_pull_none>; > > + }; > > + > > /omit-if-no-ref/ > > tsadcm0_shut: tsadcm0-shut { > > rockchip,pins = > > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > > index 77c679304916..0905fac0726a 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > > @@ -51,6 +51,7 @@ cpu0: cpu@0 { > > compatible = "arm,cortex-a55"; > > reg = <0x0 0x0>; > > clocks = <&scmi_clk 0>; > > + #cooling-cells = <2>; > > enable-method = "psci"; > > operating-points-v2 = <&cpu0_opp_table>; > > }; > > @@ -59,6 +60,7 @@ cpu1: cpu@100 { > > device_type = "cpu"; > > compatible = "arm,cortex-a55"; > > reg = <0x0 0x100>; > > + #cooling-cells = <2>; > > enable-method = "psci"; > > operating-points-v2 = <&cpu0_opp_table>; > > }; > > @@ -67,6 +69,7 @@ cpu2: cpu@200 { > > device_type = "cpu"; > > compatible = "arm,cortex-a55"; > > reg = <0x0 0x200>; > > + #cooling-cells = <2>; > > enable-method = "psci"; > > operating-points-v2 = <&cpu0_opp_table>; > > }; > > @@ -75,6 +78,7 @@ cpu3: cpu@300 { > > device_type = "cpu"; > > compatible = "arm,cortex-a55"; > > reg = <0x0 0x300>; > > + #cooling-cells = <2>; > > enable-method = "psci"; > > operating-points-v2 = <&cpu0_opp_table>; > > }; > > @@ -774,6 +778,73 @@ uart9: serial@fe6d0000 { > > status = "disabled"; > > }; > > > > + thermal_zones: thermal-zones { > > + cpu_thermal: cpu-thermal { > > + polling-delay-passive = <100>; > > + polling-delay = <1000>; > > + > > + thermal-sensors = <&tsadc 0>; > > + > > + trips { > > + cpu_alert0: cpu_alert0 { > > + temperature = <70000>; > > + hysteresis = <2000>; > > + type = "passive"; > > + }; > > + cpu_alert1: cpu_alert1 { > > + temperature = <75000>; > > + hysteresis = <2000>; > > + type = "passive"; > > + }; > > + cpu_crit: cpu_crit { > > + temperature = <95000>; > > + hysteresis = <2000>; > > + type = "critical"; > > + }; > > + }; > > + > > + cooling-maps { > > + map0 { > > + trip = <&cpu_alert0>; > > + cooling-device = > > + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > > + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > > + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > > + }; > > + }; > > + }; > > + > > + gpu_thermal: gpu-thermal { > > + polling-delay-passive = <20>; /* milliseconds */ > > + polling-delay = <1000>; /* milliseconds */ > > + > > + thermal-sensors = <&tsadc 1>; > > + }; > > + }; > > + > > + tsadc: tsadc@fe710000 { > > + compatible = "rockchip,rk3568-tsadc"; > > + reg = <0x0 0xfe710000 0x0 0x100>; > > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; > > + assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; > > + assigned-clock-rates = <17000000>, <700000>; > > + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; > > + clock-names = "tsadc", "apb_pclk"; > > + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, > > + <&cru SRST_TSADCPHY>; > > + reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; > > + rockchip,grf = <&grf>; > > + rockchip,hw-tshut-temp = <95000>; > > + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ > > + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ > > + pinctrl-names = "gpio", "otpout"; > > + pinctrl-0 = <&tsadc_gpio>; > > + pinctrl-1 = <&tsadc_shutorg>; > > The mainline thermal driver doesn't specify these pinctrl states at all. > > Heiko Oh, yes this seems to be the case. Is this something that should get fixed? In practice it likely won't ever cause problems, but in theory if someone changed the pinmux mode it could break it. > > > + #thermal-sensor-cells = <1>; > > + status = "disabled"; > > + }; > > + > > saradc: saradc@fe720000 { > > compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; > > reg = <0x0 0xfe720000 0x0 0x100>; > > > > > >
Am Mittwoch, 28. Juli 2021, 17:14:17 CEST schrieb Peter Geis: > On Wed, Jul 28, 2021 at 10:46 AM Heiko Stübner <heiko@sntech.de> wrote: > > > > Am Mittwoch, 28. Juli 2021, 15:55:30 CEST schrieb Peter Geis: > > > Add the thermal and tsadc nodes to the rk3568 device tree. > > > There are two sensors, one for the cpu, one for the gpu. > > > > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > > > --- > > > .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 6 ++ > > > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 71 +++++++++++++++++++ > > > 2 files changed, 77 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > > > index a588ca95ace2..b464c7bda1f7 100644 > > > --- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > > > +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > > > @@ -2420,6 +2420,12 @@ spi3m1_cs1: spi3m1-cs1 { > > > }; > > > > > > tsadc { > > > + /omit-if-no-ref/ > > > + tsadc_gpio: tsadc-gpio { > > > + rockchip,pins = > > > + <0 RK_PA1 0 &pcfg_pull_none>; > > > + }; > > > + > > > /omit-if-no-ref/ > > > tsadcm0_shut: tsadcm0-shut { > > > rockchip,pins = > > > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > > > index 77c679304916..0905fac0726a 100644 > > > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > > > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > > > @@ -51,6 +51,7 @@ cpu0: cpu@0 { > > > compatible = "arm,cortex-a55"; > > > reg = <0x0 0x0>; > > > clocks = <&scmi_clk 0>; > > > + #cooling-cells = <2>; > > > enable-method = "psci"; > > > operating-points-v2 = <&cpu0_opp_table>; > > > }; > > > @@ -59,6 +60,7 @@ cpu1: cpu@100 { > > > device_type = "cpu"; > > > compatible = "arm,cortex-a55"; > > > reg = <0x0 0x100>; > > > + #cooling-cells = <2>; > > > enable-method = "psci"; > > > operating-points-v2 = <&cpu0_opp_table>; > > > }; > > > @@ -67,6 +69,7 @@ cpu2: cpu@200 { > > > device_type = "cpu"; > > > compatible = "arm,cortex-a55"; > > > reg = <0x0 0x200>; > > > + #cooling-cells = <2>; > > > enable-method = "psci"; > > > operating-points-v2 = <&cpu0_opp_table>; > > > }; > > > @@ -75,6 +78,7 @@ cpu3: cpu@300 { > > > device_type = "cpu"; > > > compatible = "arm,cortex-a55"; > > > reg = <0x0 0x300>; > > > + #cooling-cells = <2>; > > > enable-method = "psci"; > > > operating-points-v2 = <&cpu0_opp_table>; > > > }; > > > @@ -774,6 +778,73 @@ uart9: serial@fe6d0000 { > > > status = "disabled"; > > > }; > > > > > > + thermal_zones: thermal-zones { > > > + cpu_thermal: cpu-thermal { > > > + polling-delay-passive = <100>; > > > + polling-delay = <1000>; > > > + > > > + thermal-sensors = <&tsadc 0>; > > > + > > > + trips { > > > + cpu_alert0: cpu_alert0 { > > > + temperature = <70000>; > > > + hysteresis = <2000>; > > > + type = "passive"; > > > + }; > > > + cpu_alert1: cpu_alert1 { > > > + temperature = <75000>; > > > + hysteresis = <2000>; > > > + type = "passive"; > > > + }; > > > + cpu_crit: cpu_crit { > > > + temperature = <95000>; > > > + hysteresis = <2000>; > > > + type = "critical"; > > > + }; > > > + }; > > > + > > > + cooling-maps { > > > + map0 { > > > + trip = <&cpu_alert0>; > > > + cooling-device = > > > + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > > > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > > > + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > > > + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > > > + }; > > > + }; > > > + }; > > > + > > > + gpu_thermal: gpu-thermal { > > > + polling-delay-passive = <20>; /* milliseconds */ > > > + polling-delay = <1000>; /* milliseconds */ > > > + > > > + thermal-sensors = <&tsadc 1>; > > > + }; > > > + }; > > > + > > > + tsadc: tsadc@fe710000 { > > > + compatible = "rockchip,rk3568-tsadc"; > > > + reg = <0x0 0xfe710000 0x0 0x100>; > > > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; > > > + assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; > > > + assigned-clock-rates = <17000000>, <700000>; > > > + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; > > > + clock-names = "tsadc", "apb_pclk"; > > > + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, > > > + <&cru SRST_TSADCPHY>; > > > + reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; > > > + rockchip,grf = <&grf>; > > > + rockchip,hw-tshut-temp = <95000>; > > > + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ > > > + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ > > > + pinctrl-names = "gpio", "otpout"; > > > + pinctrl-0 = <&tsadc_gpio>; > > > + pinctrl-1 = <&tsadc_shutorg>; > > > > The mainline thermal driver doesn't specify these pinctrl states at all. > > > > Heiko > > Oh, yes this seems to be the case. > > Is this something that should get fixed? > In practice it likely won't ever cause problems, but in theory if > someone changed the pinmux mode it could break it. take a look at for example the rk3399.dtsi where the tsadc uses the generic pinctrl names of "init" (before-probe), "default" (after probe) and "sleep" Heiko > > > > > > + #thermal-sensor-cells = <1>; > > > + status = "disabled"; > > > + }; > > > + > > > saradc: saradc@fe720000 { > > > compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; > > > reg = <0x0 0xfe720000 0x0 0x100>; > > > > > > > > > > > >
Hi Peter, On 7/28/21 3:55 PM, Peter Geis wrote: > Add the thermal and tsadc nodes to the rk3568 device tree. > There are two sensors, one for the cpu, one for the gpu. > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > --- > .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 6 ++ > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 71 +++++++++++++++++++ > 2 files changed, 77 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > index a588ca95ace2..b464c7bda1f7 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > @@ -2420,6 +2420,12 @@ spi3m1_cs1: spi3m1-cs1 { > }; > > tsadc { > + /omit-if-no-ref/ > + tsadc_gpio: tsadc-gpio { nodenames ending on -gpio -gpios are kind of reserved. Maybe use -pin or -pins. From dt-schema/schemas/gpio/gpio-consumer.yaml patternProperties: "(?<!,nr)-gpios?$": $ref: "/schemas/types.yaml#/definitions/phandle-array" > + rockchip,pins = > + <0 RK_PA1 0 &pcfg_pull_none>; > + }; > + > /omit-if-no-ref/ > tsadcm0_shut: tsadcm0-shut { > rockchip,pins = > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > index 77c679304916..0905fac0726a 100644 > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > @@ -51,6 +51,7 @@ cpu0: cpu@0 { > compatible = "arm,cortex-a55"; > reg = <0x0 0x0>; > clocks = <&scmi_clk 0>; > + #cooling-cells = <2>; > enable-method = "psci"; > operating-points-v2 = <&cpu0_opp_table>; > }; > @@ -59,6 +60,7 @@ cpu1: cpu@100 { > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x100>; > + #cooling-cells = <2>; > enable-method = "psci"; > operating-points-v2 = <&cpu0_opp_table>; > }; > @@ -67,6 +69,7 @@ cpu2: cpu@200 { > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x200>; > + #cooling-cells = <2>; > enable-method = "psci"; > operating-points-v2 = <&cpu0_opp_table>; > }; > @@ -75,6 +78,7 @@ cpu3: cpu@300 { > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x300>; > + #cooling-cells = <2>; > enable-method = "psci"; > operating-points-v2 = <&cpu0_opp_table>; > }; > @@ -774,6 +778,73 @@ uart9: serial@fe6d0000 { > status = "disabled"; > }; > > + thermal_zones: thermal-zones { > + cpu_thermal: cpu-thermal { > + polling-delay-passive = <100>; > + polling-delay = <1000>; > + > + thermal-sensors = <&tsadc 0>; > + > + trips { > + cpu_alert0: cpu_alert0 { > + temperature = <70000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + cpu_alert1: cpu_alert1 { > + temperature = <75000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + cpu_crit: cpu_crit { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "critical"; > + }; > + }; > + > + cooling-maps { > + map0 { > + trip = <&cpu_alert0>; > + cooling-device = > + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + }; > + > + gpu_thermal: gpu-thermal { > + polling-delay-passive = <20>; /* milliseconds */ > + polling-delay = <1000>; /* milliseconds */ > + > + thermal-sensors = <&tsadc 1>; > + }; > + }; > + > + tsadc: tsadc@fe710000 { > + compatible = "rockchip,rk3568-tsadc"; > + reg = <0x0 0xfe710000 0x0 0x100>; > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; > + assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; > + assigned-clock-rates = <17000000>, <700000>; > + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; > + clock-names = "tsadc", "apb_pclk"; > + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, > + <&cru SRST_TSADCPHY>; > + reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; > + rockchip,grf = <&grf>; > + rockchip,hw-tshut-temp = <95000>; > + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ > + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ > + pinctrl-names = "gpio", "otpout"; > + pinctrl-0 = <&tsadc_gpio>; > + pinctrl-1 = <&tsadc_shutorg>; > + #thermal-sensor-cells = <1>; > + status = "disabled"; > + }; > + > saradc: saradc@fe720000 { > compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; > reg = <0x0 0xfe720000 0x0 0x100>; >
> Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 28.07.2021, o godz. 15:55: > > Add the thermal and tsadc nodes to the rk3568 device tree. > There are two sensors, one for the cpu, one for the gpu. > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > --- > .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 6 ++ > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 71 +++++++++++++++++++ > 2 files changed, 77 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > index a588ca95ace2..b464c7bda1f7 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > @@ -2420,6 +2420,12 @@ spi3m1_cs1: spi3m1-cs1 { > }; > > tsadc { > + /omit-if-no-ref/ > + tsadc_gpio: tsadc-gpio { > + rockchip,pins = > + <0 RK_PA1 0 &pcfg_pull_none>; > + }; > + > /omit-if-no-ref/ > tsadcm0_shut: tsadcm0-shut { > rockchip,pins = > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > index 77c679304916..0905fac0726a 100644 > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > @@ -51,6 +51,7 @@ cpu0: cpu@0 { > compatible = "arm,cortex-a55"; > reg = <0x0 0x0>; > clocks = <&scmi_clk 0>; > + #cooling-cells = <2>; > enable-method = "psci"; > operating-points-v2 = <&cpu0_opp_table>; > }; > @@ -59,6 +60,7 @@ cpu1: cpu@100 { > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x100>; > + #cooling-cells = <2>; > enable-method = "psci"; > operating-points-v2 = <&cpu0_opp_table>; > }; > @@ -67,6 +69,7 @@ cpu2: cpu@200 { > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x200>; > + #cooling-cells = <2>; > enable-method = "psci"; > operating-points-v2 = <&cpu0_opp_table>; > }; > @@ -75,6 +78,7 @@ cpu3: cpu@300 { > device_type = "cpu"; > compatible = "arm,cortex-a55"; > reg = <0x0 0x300>; > + #cooling-cells = <2>; > enable-method = "psci"; > operating-points-v2 = <&cpu0_opp_table>; > }; > @@ -774,6 +778,73 @@ uart9: serial@fe6d0000 { > status = "disabled"; > }; > > + thermal_zones: thermal-zones { > + cpu_thermal: cpu-thermal { > + polling-delay-passive = <100>; > + polling-delay = <1000>; > + > + thermal-sensors = <&tsadc 0>; > + > + trips { > + cpu_alert0: cpu_alert0 { > + temperature = <70000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + cpu_alert1: cpu_alert1 { > + temperature = <75000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + cpu_crit: cpu_crit { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "critical"; > + }; > + }; > + > + cooling-maps { > + map0 { > + trip = <&cpu_alert0>; > + cooling-device = > + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + }; > + > + gpu_thermal: gpu-thermal { > + polling-delay-passive = <20>; /* milliseconds */ > + polling-delay = <1000>; /* milliseconds */ > + > + thermal-sensors = <&tsadc 1>; > + }; > + }; > + > + tsadc: tsadc@fe710000 { > + compatible = "rockchip,rk3568-tsadc"; > + reg = <0x0 0xfe710000 0x0 0x100>; > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; > + assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; > + assigned-clock-rates = <17000000>, <700000>; > + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; > + clock-names = "tsadc", "apb_pclk"; > + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, > + <&cru SRST_TSADCPHY>; > + reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; > + rockchip,grf = <&grf>; > + rockchip,hw-tshut-temp = <95000>; > + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ > + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ > + pinctrl-names = "gpio", "otpout"; > + pinctrl-0 = <&tsadc_gpio>; > + pinctrl-1 = <&tsadc_shutorg>; > + #thermal-sensor-cells = <1>; > + status = "disabled"; > + }; > + > saradc: saradc@fe720000 { > compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; > reg = <0x0 0xfe720000 0x0 0x100>; > -- > 2.25.1 > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip Peter, I'm trying to use this series to get thermal on rk3566 based tvbox (x96-x6). Driver loads but i'm getting following error: [ 132.873979] rockchip-thermal fe710000.tsadc: failed to register sensor 0: -517 [ 132.874650] rockchip-thermal fe710000.tsadc: failed to register sensor[0] : error = -517 Maybe you have some hints here?
On Mon, Jan 17, 2022 at 3:43 AM Piotr Oniszczuk <piotr.oniszczuk@gmail.com> wrote: > > > > > Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 28.07.2021, o godz. 15:55: > > > > Add the thermal and tsadc nodes to the rk3568 device tree. > > There are two sensors, one for the cpu, one for the gpu. > > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > > --- > > .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 6 ++ > > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 71 +++++++++++++++++++ > > 2 files changed, 77 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > > index a588ca95ace2..b464c7bda1f7 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > > +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > > @@ -2420,6 +2420,12 @@ spi3m1_cs1: spi3m1-cs1 { > > }; > > > > tsadc { > > + /omit-if-no-ref/ > > + tsadc_gpio: tsadc-gpio { > > + rockchip,pins = > > + <0 RK_PA1 0 &pcfg_pull_none>; > > + }; > > + > > /omit-if-no-ref/ > > tsadcm0_shut: tsadcm0-shut { > > rockchip,pins = > > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > > index 77c679304916..0905fac0726a 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > > @@ -51,6 +51,7 @@ cpu0: cpu@0 { > > compatible = "arm,cortex-a55"; > > reg = <0x0 0x0>; > > clocks = <&scmi_clk 0>; > > + #cooling-cells = <2>; > > enable-method = "psci"; > > operating-points-v2 = <&cpu0_opp_table>; > > }; > > @@ -59,6 +60,7 @@ cpu1: cpu@100 { > > device_type = "cpu"; > > compatible = "arm,cortex-a55"; > > reg = <0x0 0x100>; > > + #cooling-cells = <2>; > > enable-method = "psci"; > > operating-points-v2 = <&cpu0_opp_table>; > > }; > > @@ -67,6 +69,7 @@ cpu2: cpu@200 { > > device_type = "cpu"; > > compatible = "arm,cortex-a55"; > > reg = <0x0 0x200>; > > + #cooling-cells = <2>; > > enable-method = "psci"; > > operating-points-v2 = <&cpu0_opp_table>; > > }; > > @@ -75,6 +78,7 @@ cpu3: cpu@300 { > > device_type = "cpu"; > > compatible = "arm,cortex-a55"; > > reg = <0x0 0x300>; > > + #cooling-cells = <2>; > > enable-method = "psci"; > > operating-points-v2 = <&cpu0_opp_table>; > > }; > > @@ -774,6 +778,73 @@ uart9: serial@fe6d0000 { > > status = "disabled"; > > }; > > > > + thermal_zones: thermal-zones { > > + cpu_thermal: cpu-thermal { > > + polling-delay-passive = <100>; > > + polling-delay = <1000>; > > + > > + thermal-sensors = <&tsadc 0>; > > + > > + trips { > > + cpu_alert0: cpu_alert0 { > > + temperature = <70000>; > > + hysteresis = <2000>; > > + type = "passive"; > > + }; > > + cpu_alert1: cpu_alert1 { > > + temperature = <75000>; > > + hysteresis = <2000>; > > + type = "passive"; > > + }; > > + cpu_crit: cpu_crit { > > + temperature = <95000>; > > + hysteresis = <2000>; > > + type = "critical"; > > + }; > > + }; > > + > > + cooling-maps { > > + map0 { > > + trip = <&cpu_alert0>; > > + cooling-device = > > + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > > + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > > + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > > + }; > > + }; > > + }; > > + > > + gpu_thermal: gpu-thermal { > > + polling-delay-passive = <20>; /* milliseconds */ > > + polling-delay = <1000>; /* milliseconds */ > > + > > + thermal-sensors = <&tsadc 1>; > > + }; > > + }; > > + > > + tsadc: tsadc@fe710000 { > > + compatible = "rockchip,rk3568-tsadc"; > > + reg = <0x0 0xfe710000 0x0 0x100>; > > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; > > + assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; > > + assigned-clock-rates = <17000000>, <700000>; > > + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; > > + clock-names = "tsadc", "apb_pclk"; > > + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, > > + <&cru SRST_TSADCPHY>; > > + reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; > > + rockchip,grf = <&grf>; > > + rockchip,hw-tshut-temp = <95000>; > > + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ > > + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ > > + pinctrl-names = "gpio", "otpout"; > > + pinctrl-0 = <&tsadc_gpio>; > > + pinctrl-1 = <&tsadc_shutorg>; > > + #thermal-sensor-cells = <1>; > > + status = "disabled"; > > + }; > > + > > saradc: saradc@fe720000 { > > compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; > > reg = <0x0 0xfe720000 0x0 0x100>; > > -- > > 2.25.1 > > > > > > _______________________________________________ > > Linux-rockchip mailing list > > Linux-rockchip@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-rockchip > > Peter, > > I'm trying to use this series to get thermal on rk3566 based tvbox (x96-x6). > Driver loads but i'm getting following error: > > [ 132.873979] rockchip-thermal fe710000.tsadc: failed to register sensor 0: -517 > [ 132.874650] rockchip-thermal fe710000.tsadc: failed to register sensor[0] : error = -517 > > Maybe you have some hints here? Error -517 means -EPROBE_DEFER, a device it relies on hasn't probed. TSADC doesn't directly rely on anything that shouldn't already be enabled. (Pinctrl, clocks, and grf all break a lot more than tsadc if disabled) Does your kernel config have all of the rockchip elements enabled? > >
> Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 17.01.2022, o godz. 14:49: > >> >> Peter, >> >> I'm trying to use this series to get thermal on rk3566 based tvbox (x96-x6). >> Driver loads but i'm getting following error: >> >> [ 132.873979] rockchip-thermal fe710000.tsadc: failed to register sensor 0: -517 >> [ 132.874650] rockchip-thermal fe710000.tsadc: failed to register sensor[0] : error = -517 >> >> Maybe you have some hints here? > > Error -517 means -EPROBE_DEFER, a device it relies on hasn't probed. > TSADC doesn't directly rely on anything that shouldn't already be > enabled. (Pinctrl, clocks, and grf all break a lot more than tsadc if > disabled) > Does your kernel config have all of the rockchip elements enabled? > Peter, For sure I can't say 'yes' with 100% confidence. I'm trying do my best for rk3566 (currently have working: SD/Eth/HDMI/Sound/USB2port0/BT). Maybe you may point me pls for good reference of rk356x defconfig? btw: a bit of context: In my application (https://github.com/warpme/minimyth2) i have target to have single OS binary for all supported Allwinner/Amlogic/Rockchip/Broadcom devices. By this kernel config i'm using is painfully assembled to have minimal working kernel for all targets. It's a painful road....but still want to go this route for: minimal image size; shortest build time & one-for-all binary. my current config: https://github.com/warpme/minimyth2/blob/master/script/kernel/linux-5.16/files/linux-5.16-arm64-armv8.config btw2: for rk3566 i'm using majority of your patches! Great work of you!
On Mon, Jan 17, 2022 at 9:13 AM Piotr Oniszczuk <piotr.oniszczuk@gmail.com> wrote: > > > > > Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 17.01.2022, o godz. 14:49: > > > >> > >> Peter, > >> > >> I'm trying to use this series to get thermal on rk3566 based tvbox (x96-x6). > >> Driver loads but i'm getting following error: > >> > >> [ 132.873979] rockchip-thermal fe710000.tsadc: failed to register sensor 0: -517 > >> [ 132.874650] rockchip-thermal fe710000.tsadc: failed to register sensor[0] : error = -517 > >> > >> Maybe you have some hints here? > > > > Error -517 means -EPROBE_DEFER, a device it relies on hasn't probed. > > TSADC doesn't directly rely on anything that shouldn't already be > > enabled. (Pinctrl, clocks, and grf all break a lot more than tsadc if > > disabled) > > Does your kernel config have all of the rockchip elements enabled? > > > > Peter, > For sure I can't say 'yes' with 100% confidence. > I'm trying do my best for rk3566 (currently have working: SD/Eth/HDMI/Sound/USB2port0/BT). > > Maybe you may point me pls for good reference of rk356x defconfig? > > btw: a bit of context: > In my application (https://github.com/warpme/minimyth2) i have target to have single OS binary for all supported Allwinner/Amlogic/Rockchip/Broadcom devices. > By this kernel config i'm using is painfully assembled to have minimal working kernel for all targets. > It's a painful road....but still want to go this route for: minimal image size; shortest build time & one-for-all binary. > my current config: https://github.com/warpme/minimyth2/blob/master/script/kernel/linux-5.16/files/linux-5.16-arm64-armv8.config I recommend you use `make savedefconfig`. It produces a simplified defconfig based on your .config. Your issue is in your dts. You have retained the quartz64-a &cpu_thermal active thermal node without tying in an active thermal control device (a fan). By default the rk356x dtsi passive thermal trips are hooked up and will throttle the device in case of overtemp. If your device has no active thermal control, you don't need to add the &cpu_thermal node at all to your dts. > > btw2: for rk3566 i'm using majority of your patches! > Great work of you! > > > > > > >
> Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 17.01.2022, o godz. 15:38: > > > > Your issue is in your dts. > You have retained the quartz64-a &cpu_thermal active thermal node > without tying in an active thermal control device (a fan). > By default the rk356x dtsi passive thermal trips are hooked up and > will throttle the device in case of overtemp. > If your device has no active thermal control, you don't need to add > the &cpu_thermal node at all to your dts. > >> >> btw2: for rk3566 i'm using majority of your patches! >> Great work of you! Peter, Many thx! Now it works nicely: cpu_thermal-virtual-0 Adapter: Virtual device temp1: +33.8°C (crit = +95.0°C) gpu_thermal-virtual-0 Adapter: Virtual device temp1: +34.4°C (crit = +95.0°C) again: many thx! forgive me unrelated q: may hint me for script you are using in your gitlab ci for building quartz64 u-boot in ci pipeline? I'm using yours binaries - but want to add building from sources in my project....
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi index a588ca95ace2..b464c7bda1f7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi @@ -2420,6 +2420,12 @@ spi3m1_cs1: spi3m1-cs1 { }; tsadc { + /omit-if-no-ref/ + tsadc_gpio: tsadc-gpio { + rockchip,pins = + <0 RK_PA1 0 &pcfg_pull_none>; + }; + /omit-if-no-ref/ tsadcm0_shut: tsadcm0-shut { rockchip,pins = diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 77c679304916..0905fac0726a 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -51,6 +51,7 @@ cpu0: cpu@0 { compatible = "arm,cortex-a55"; reg = <0x0 0x0>; clocks = <&scmi_clk 0>; + #cooling-cells = <2>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; }; @@ -59,6 +60,7 @@ cpu1: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x100>; + #cooling-cells = <2>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; }; @@ -67,6 +69,7 @@ cpu2: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x200>; + #cooling-cells = <2>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; }; @@ -75,6 +78,7 @@ cpu3: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x300>; + #cooling-cells = <2>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; }; @@ -774,6 +778,73 @@ uart9: serial@fe6d0000 { status = "disabled"; }; + thermal_zones: thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <100>; + polling-delay = <1000>; + + thermal-sensors = <&tsadc 0>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + }; + }; + + tsadc: tsadc@fe710000 { + compatible = "rockchip,rk3568-tsadc"; + reg = <0x0 0xfe710000 0x0 0x100>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; + assigned-clock-rates = <17000000>, <700000>; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, + <&cru SRST_TSADCPHY>; + reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; + rockchip,grf = <&grf>; + rockchip,hw-tshut-temp = <95000>; + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_gpio>; + pinctrl-1 = <&tsadc_shutorg>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + saradc: saradc@fe720000 { compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; reg = <0x0 0xfe720000 0x0 0x100>;
Add the thermal and tsadc nodes to the rk3568 device tree. There are two sensors, one for the cpu, one for the gpu. Signed-off-by: Peter Geis <pgwipeout@gmail.com> --- .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 6 ++ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 71 +++++++++++++++++++ 2 files changed, 77 insertions(+)