| Message ID | 20210728161020.3905-3-michael.riesch@wolfvision.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | add ethernet support to rk3568 dts | expand |
Hi Michael, On 7/28/21 6:10 PM, Michael Riesch wrote: > Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> > --- > .../boot/dts/rockchip/rk3568-evb1-v10.dts | 69 +++++++++++++++++++ > 1 file changed, 69 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts > index 69786557093d..8f4c40d71914 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts > +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts > @@ -13,6 +13,11 @@ > model = "Rockchip RK3568 EVB1 DDR4 V10 Board"; > compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568"; > > + aliases { > + ethernet0 = &gmac0; > + ethernet1 = &gmac1; > + }; > + > chosen: chosen { > stdout-path = "serial2:1500000n8"; > }; > @@ -67,6 +72,70 @@ > }; > }; > > +&gmac0 { > + phy-mode = "rgmii"; > + clock_in_out = "output"; > + > + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; > + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; > + assigned-clock-rates = <0>, <125000000>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&gmac0_miim > + &gmac0_tx_bus2 > + &gmac0_rx_bus2 > + &gmac0_rgmii_clk > + &gmac0_rgmii_bus>; > + > + tx_delay = <0x3c>; > + rx_delay = <0x2f>; > + > + phy-handle = <&rgmii_phy0>; > + status = "okay"; > +}; > + > +&gmac1 { > + phy-mode = "rgmii"; > + clock_in_out = "output"; > + > + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; > + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; > + assigned-clock-rates = <0>, <125000000>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&gmac1m1_miim > + &gmac1m1_tx_bus2 > + &gmac1m1_rx_bus2 > + &gmac1m1_rgmii_clk > + &gmac1m1_rgmii_bus>; > + > + tx_delay = <0x4f>; > + rx_delay = <0x26>; > + > + phy-handle = <&rgmii_phy1>; > + status = "okay"; > +}; > + > +&mdio0 { > + rgmii_phy0: phy@0 { Could you test with ethernet-phy.yaml? $nodename: pattern: "^ethernet-phy(@[a-f0-9]+)?$" > + compatible = "ethernet-phy-ieee802.3-c22"; > + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; > + reset-assert-us = <20000>; > + reset-deassert-us = <100000>; > + reg = <0x0>; Sort order is: compatible reg (interrupts) The rest in alphabetical order. > + }; > +}; > + > +&mdio1 { > + rgmii_phy1: phy@0 { dito > + compatible = "ethernet-phy-ieee802.3-c22"; > + reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; > + reset-assert-us = <20000>; > + reset-deassert-us = <100000>; > + reg = <0x0>; dito > + }; > +}; > + > &sdhci { > bus-width = <8>; > max-frequency = <200000000>; >
On Wed, Jul 28, 2021 at 06:10:20PM +0200, Michael Riesch wrote: > +&gmac0 { > + phy-mode = "rgmii"; ... > + > + tx_delay = <0x3c>; > + rx_delay = <0x2f>; Hi Michael In general, we try to have the PHY introduce the RGMII delays, not the MAC. Did you try phy-mode = "rgmii-id"; and remove these delay values? It is hard for me to say if that will work because i've no idea what 0x3c and 0x2f means? Are they equivalent to 2ns? Andrew
On Wed, Jul 28, 2021 at 1:55 PM Andrew Lunn <andrew@lunn.ch> wrote: > > On Wed, Jul 28, 2021 at 06:10:20PM +0200, Michael Riesch wrote: > > +&gmac0 { > > + phy-mode = "rgmii"; > > ... > > + > > + tx_delay = <0x3c>; > > + rx_delay = <0x2f>; > > Hi Michael > > In general, we try to have the PHY introduce the RGMII delays, not the > MAC. Did you try > > phy-mode = "rgmii-id"; > > and remove these delay values? It is hard for me to say if that will > work because i've no idea what 0x3c and 0x2f means? Are they > equivalent to 2ns? Unfortunately the driver and TRM are both rather non-specific as to how this works. The driver sets the tx_delay to 0x30 and rx_delay to 0x10 if these values are not defined, or sets them both to 0 in case of rgmii_id. Generally all rockchip boards use this value instead of the rgmii_id, I imagine because it's more consistent to tune here than the hit or miss support of the phy drivers. The usual course of action is to test to find the lowest and highest working values and take the median value to plug in here. > > Andrew
> Generally all rockchip boards use this value instead of the rgmii_id, > I imagine because it's more consistent to tune here than the hit or > miss support of the phy drivers. Most PHY drivers actually implement it correctly, since by default, most systems get the PHY to do the delays. But if most Rockchip boards do it this way, there is a lot to be said for consistence, so this is fine by me. Andrew
Hello Andrew, Peter, On 7/28/21 10:37 PM, Andrew Lunn wrote: >> Generally all rockchip boards use this value instead of the rgmii_id, >> I imagine because it's more consistent to tune here than the hit or >> miss support of the phy drivers. > > Most PHY drivers actually implement it correctly, since by default, > most systems get the PHY to do the delays. > > But if most Rockchip boards do it this way, there is a lot to be said > for consistence, so this is fine by me. I have tested a dts without the delays and with phy-mode = "rgmii-id" and it seems to work just fine. Although consistency with other Rockchip boards is something one should consider, I think I'll go along the "rgmii-id" path since this seems to be a more general convention. Thanks for your comments, I'll submit a v2. Regards, Michael
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts index 69786557093d..8f4c40d71914 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts @@ -13,6 +13,11 @@ model = "Rockchip RK3568 EVB1 DDR4 V10 Board"; compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568"; + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + }; + chosen: chosen { stdout-path = "serial2:1500000n8"; }; @@ -67,6 +72,70 @@ }; }; +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x3c>; + rx_delay = <0x2f>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x26>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reg = <0x0>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reg = <0x0>; + }; +}; + &sdhci { bus-width = <8>; max-frequency = <200000000>;
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> --- .../boot/dts/rockchip/rk3568-evb1-v10.dts | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+)