| Message ID | 20210721090706.21523-6-james.clark@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Support ETE decoding | expand |
On Wed, Jul 21, 2021 at 10:07:04AM +0100, James Clark wrote: > If the TRCDEVARCH register was saved, and it shows that ETE is present, > then instantiate an OCSD_BUILTIN_DCD_ETE decoder instead of > OCSD_BUILTIN_DCD_ETMV4I. ETE is the new trace feature for Armv9. > > Testing performed > ================= > > * Old files with v0 headers still open correctly > * Old files with v1 headers with no TRCDEVARCH saved still open > * New files with TRCDEVARCH open using an old version of perf that > supports v1 headers > * Coresight decoding results in the same output if there are no new ETE > packet types > > Signed-off-by: James Clark <james.clark@arm.com> > --- > .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 29 ++++++++++- > .../perf/util/cs-etm-decoder/cs-etm-decoder.h | 7 +++ > tools/perf/util/cs-etm.c | 49 ++++++++++++++++++- > tools/perf/util/cs-etm.h | 1 + > 4 files changed, 82 insertions(+), 4 deletions(-) > > diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c > index 60147c908425..37bc9d6a7677 100644 > --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c > +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c > @@ -127,8 +127,12 @@ static int cs_etm_decoder__gen_etmv3_config(struct cs_etm_trace_params *params, > #define TRCIDR1_TRCARCHMIN_SHIFT 4 > #define TRCIDR1_TRCARCHMIN_MASK GENMASK(7, 4) > #define TRCIDR1_TRCARCHMIN(x) (((x) & TRCIDR1_TRCARCHMIN_MASK) >> TRCIDR1_TRCARCHMIN_SHIFT) > -static enum _ocsd_arch_version cs_etm_decoder__get_arch_ver(u32 reg_idr1) > +static enum _ocsd_arch_version cs_etm_decoder__get_arch_ver(u32 reg_idr1, u32 reg_devarch) > { > + /* ETE has to be v9 so set arch version to v8.3+ (ARCH__AA64) */ > + if (cs_etm__is_ete(reg_devarch)) > + return ARCH_AA64; > + Based on values used in below change, I think we can unify the ETM versio number like: ARCH_V8R3 : REVISION, bits[19:16] is 0x3 ARCH_V8R4 : REVISION, bits[19:16] is 0x4 ARCH_V8R5 : REVISION, bits[19:16] is 0x5 > /* > * If the ETM trace minor version is 4 or more then we can assume > * the architecture is ARCH_AA64 rather than just V8 > @@ -150,7 +154,22 @@ static void cs_etm_decoder__gen_etmv4_config(struct cs_etm_trace_params *params, > config->reg_idr11 = 0; > config->reg_idr12 = 0; > config->reg_idr13 = 0; > - config->arch_ver = cs_etm_decoder__get_arch_ver(params->etmv4.reg_idr1); > + config->arch_ver = cs_etm_decoder__get_arch_ver(params->etmv4.reg_idr1, 0); Can we always pass the value "params->ete.reg_devarch" rather than directly pass "0"? > + config->core_prof = profile_CortexA; > +} > + > +static void cs_etm_decoder__gen_ete_config(struct cs_etm_trace_params *params, > + ocsd_ete_cfg *config) > +{ > + config->reg_configr = params->ete.base_params.reg_configr; > + config->reg_traceidr = params->ete.base_params.reg_traceidr; > + config->reg_idr0 = params->ete.base_params.reg_idr0; > + config->reg_idr1 = params->ete.base_params.reg_idr1; > + config->reg_idr2 = params->ete.base_params.reg_idr2; > + config->reg_idr8 = params->ete.base_params.reg_idr8; > + config->reg_devarch = params->ete.reg_devarch; > + config->arch_ver = cs_etm_decoder__get_arch_ver(params->ete.base_params.reg_idr1, > + params->ete.reg_devarch); > config->core_prof = profile_CortexA; > } > > @@ -598,6 +617,7 @@ cs_etm_decoder__create_etm_decoder(struct cs_etm_decoder_params *d_params, > const char *decoder_name; > ocsd_etmv3_cfg config_etmv3; > ocsd_etmv4_cfg trace_config_etmv4; > + ocsd_ete_cfg trace_config_ete; > void *trace_config; > u8 csid; > > @@ -615,6 +635,11 @@ cs_etm_decoder__create_etm_decoder(struct cs_etm_decoder_params *d_params, > decoder_name = OCSD_BUILTIN_DCD_ETMV4I; > trace_config = &trace_config_etmv4; > break; > + case CS_ETM_PROTO_ETE: > + cs_etm_decoder__gen_ete_config(t_params, &trace_config_ete); > + decoder_name = OCSD_BUILTIN_DCD_ETE; > + trace_config = &trace_config_ete; > + break; > default: > return -1; > } > diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h > index 11f3391d06f2..9137796fe3c5 100644 > --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h > +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h > @@ -37,11 +37,17 @@ struct cs_etmv4_trace_params { > u32 reg_traceidr; > }; > > +struct cs_ete_trace_params { > + struct cs_etmv4_trace_params base_params; > + u32 reg_devarch; As we have said, can we directly support ETMv4.5, so that it can smoothly support ETE features? If so, we don't need to add a new structure "cs_ete_trace_params" at here. > +}; > + > struct cs_etm_trace_params { > int protocol; > union { > struct cs_etmv3_trace_params etmv3; > struct cs_etmv4_trace_params etmv4; > + struct cs_ete_trace_params ete; > }; > }; > > @@ -65,6 +71,7 @@ enum { > CS_ETM_PROTO_ETMV4i, > CS_ETM_PROTO_ETMV4d, > CS_ETM_PROTO_PTM, > + CS_ETM_PROTO_ETE > }; > > enum cs_etm_decoder_operation { > diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c > index 68978f6707a8..870073bce670 100644 > --- a/tools/perf/util/cs-etm.c > +++ b/tools/perf/util/cs-etm.c > @@ -460,11 +460,44 @@ static void cs_etm__set_trace_param_etmv4(struct cs_etm_trace_params *t_params, > t_params[idx].etmv4.reg_traceidr = metadata[idx][CS_ETMV4_TRCTRACEIDR]; > } > > +static void cs_etm__set_trace_param_ete(struct cs_etm_trace_params *t_params, > + struct cs_etm_auxtrace *etm, int idx) > +{ > + u64 **metadata = etm->metadata; > + > + t_params[idx].protocol = CS_ETM_PROTO_ETE; > + t_params[idx].ete.base_params.reg_idr0 = metadata[idx][CS_ETMV4_TRCIDR0]; > + t_params[idx].ete.base_params.reg_idr1 = metadata[idx][CS_ETMV4_TRCIDR1]; > + t_params[idx].ete.base_params.reg_idr2 = metadata[idx][CS_ETMV4_TRCIDR2]; > + t_params[idx].ete.base_params.reg_idr8 = metadata[idx][CS_ETMV4_TRCIDR8]; > + t_params[idx].ete.base_params.reg_configr = metadata[idx][CS_ETMV4_TRCCONFIGR]; > + t_params[idx].ete.base_params.reg_traceidr = metadata[idx][CS_ETMV4_TRCTRACEIDR]; > + t_params[idx].ete.reg_devarch = metadata[idx][CS_ETE_TRCDEVARCH]; > +} > + > +#define TRCDEVARCH_ARCHPART_SHIFT 0 > +#define TRCDEVARCH_ARCHPART_MASK GENMASK(11, 0) > +#define TRCDEVARCH_ARCHPART(x) (((x) & TRCDEVARCH_ARCHPART_MASK) >> TRCDEVARCH_ARCHPART_SHIFT) > + > +#define TRCDEVARCH_ARCHVER_SHIFT 12 > +#define TRCDEVARCH_ARCHVER_MASK GENMASK(15, 12) > +#define TRCDEVARCH_ARCHVER(x) (((x) & TRCDEVARCH_ARCHVER_MASK) >> TRCDEVARCH_ARCHVER_SHIFT) > + > +bool cs_etm__is_ete(u32 trcdevarch) > +{ > + /* > + * ETE if ARCHVER is 5 (ARCHVER is 4 for ETM) and ARCHPART is 0xA13. > + * See ETM_DEVARCH_ETE_ARCH in coresight-etm4x.h > + */ > + return TRCDEVARCH_ARCHVER(trcdevarch) == 5 && TRCDEVARCH_ARCHPART(trcdevarch) == 0xA13; I think this is incorrect. Here should check the bit field "REVISION, bits[19:16]". If it's field value is >= 5, then we can say it supports ETE. I checked the spec for ETMv4.4 and ETMv4.6, both use the same values for the Bits[15:12] = 0x4, so the architecture ID is same for ETMv4.x IPs. Thanks, Leo > +} > + > + > static int cs_etm__init_trace_params(struct cs_etm_trace_params *t_params, > struct cs_etm_auxtrace *etm, > int decoders_per_cpu) > { > - int i; > + int i, num_params; > u32 etmidr; > u64 architecture; > > @@ -477,7 +510,19 @@ static int cs_etm__init_trace_params(struct cs_etm_trace_params *t_params, > cs_etm__set_trace_param_etmv3(t_params, etm, i, etmidr); > break; > case __perf_cs_etmv4_magic: > - cs_etm__set_trace_param_etmv4(t_params, etm, i); > + /* > + * If devarch was saved and shows ETE, initialise ETE decoder. Otherwise > + * ETM decoder will still be able to decode a subset of the data. The total > + * number of params is number of params saved + common block size for v1, > + * see cs_etm_get_metadata(). > + */ > + num_params = etm->metadata[i][CS_ETM_NR_TRC_PARAMS] + > + CS_ETM_COMMON_BLK_MAX_V1; > + if (num_params > CS_ETE_TRCDEVARCH && > + cs_etm__is_ete(etm->metadata[i][CS_ETE_TRCDEVARCH])) > + cs_etm__set_trace_param_ete(t_params, etm, i); > + else > + cs_etm__set_trace_param_etmv4(t_params, etm, i); > break; > default: > return -EINVAL; > diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h > index 52d82dce9d59..514083819657 100644 > --- a/tools/perf/util/cs-etm.h > +++ b/tools/perf/util/cs-etm.h > @@ -203,6 +203,7 @@ void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq, > u8 trace_chan_id); > struct cs_etm_packet_queue > *cs_etm__etmq_get_packet_queue(struct cs_etm_queue *etmq, u8 trace_chan_id); > +bool cs_etm__is_ete(u32 trcdevarch); > #else > static inline int > cs_etm__process_auxtrace_info(union perf_event *event __maybe_unused, > -- > 2.28.0 >
On 31/07/2021 08:23, Leo Yan wrote: > On Wed, Jul 21, 2021 at 10:07:04AM +0100, James Clark wrote: >> If the TRCDEVARCH register was saved, and it shows that ETE is present, >> then instantiate an OCSD_BUILTIN_DCD_ETE decoder instead of >> OCSD_BUILTIN_DCD_ETMV4I. ETE is the new trace feature for Armv9. >> >> Testing performed >> ================= >> >> * Old files with v0 headers still open correctly >> * Old files with v1 headers with no TRCDEVARCH saved still open >> * New files with TRCDEVARCH open using an old version of perf that >> supports v1 headers >> * Coresight decoding results in the same output if there are no new ETE >> packet types >> >> Signed-off-by: James Clark <james.clark@arm.com> >> --- >> .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 29 ++++++++++- >> .../perf/util/cs-etm-decoder/cs-etm-decoder.h | 7 +++ >> tools/perf/util/cs-etm.c | 49 ++++++++++++++++++- >> tools/perf/util/cs-etm.h | 1 + >> 4 files changed, 82 insertions(+), 4 deletions(-) >> >> diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c >> index 60147c908425..37bc9d6a7677 100644 >> --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c >> +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c >> @@ -127,8 +127,12 @@ static int cs_etm_decoder__gen_etmv3_config(struct cs_etm_trace_params *params, >> #define TRCIDR1_TRCARCHMIN_SHIFT 4 >> #define TRCIDR1_TRCARCHMIN_MASK GENMASK(7, 4) >> #define TRCIDR1_TRCARCHMIN(x) (((x) & TRCIDR1_TRCARCHMIN_MASK) >> TRCIDR1_TRCARCHMIN_SHIFT) >> -static enum _ocsd_arch_version cs_etm_decoder__get_arch_ver(u32 reg_idr1) >> +static enum _ocsd_arch_version cs_etm_decoder__get_arch_ver(u32 reg_idr1, u32 reg_devarch) >> { >> + /* ETE has to be v9 so set arch version to v8.3+ (ARCH__AA64) */ >> + if (cs_etm__is_ete(reg_devarch)) >> + return ARCH_AA64; >> + > > Based on values used in below change, I think we can unify the ETM > versio number like: > > ARCH_V8R3 : REVISION, bits[19:16] is 0x3 > ARCH_V8R4 : REVISION, bits[19:16] is 0x4 > ARCH_V8R5 : REVISION, bits[19:16] is 0x5 Do you mean make this change in OpenCSD? At the moment it understands these values so I'm not sure if the extra ones would be useful: /** Core Architecture Version */ typedef enum _ocsd_arch_version { ARCH_UNKNOWN = 0x0000, /**< unknown architecture */ ARCH_CUSTOM = 0x0001, /**< None ARM, custom architecture */ ARCH_V7 = 0x0700, /**< V7 architecture */ ARCH_V8 = 0x0800, /**< V8 architecture */ ARCH_V8r3 = 0x0803, /**< V8.3 architecture */ ARCH_AA64 = 0x0864, /**< Min v8r3 plus additional AA64 PE features */ ARCH_V8_max = ARCH_AA64, } ocsd_arch_version_t; [...] >> diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h >> index 11f3391d06f2..9137796fe3c5 100644 >> --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h >> +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h >> @@ -37,11 +37,17 @@ struct cs_etmv4_trace_params { >> u32 reg_traceidr; >> }; >> >> +struct cs_ete_trace_params { >> + struct cs_etmv4_trace_params base_params; >> + u32 reg_devarch; > > As we have said, can we directly support ETMv4.5, so that it can > smoothly support ETE features? If so, we don't need to add a new > structure "cs_ete_trace_params" at here. > I think with the new magic number change this is more likely to stay, what are your thoughts? [...] >> + >> +#define TRCDEVARCH_ARCHPART_SHIFT 0 >> +#define TRCDEVARCH_ARCHPART_MASK GENMASK(11, 0) >> +#define TRCDEVARCH_ARCHPART(x) (((x) & TRCDEVARCH_ARCHPART_MASK) >> TRCDEVARCH_ARCHPART_SHIFT) >> + >> +#define TRCDEVARCH_ARCHVER_SHIFT 12 >> +#define TRCDEVARCH_ARCHVER_MASK GENMASK(15, 12) >> +#define TRCDEVARCH_ARCHVER(x) (((x) & TRCDEVARCH_ARCHVER_MASK) >> TRCDEVARCH_ARCHVER_SHIFT) >> + >> +bool cs_etm__is_ete(u32 trcdevarch) >> +{ >> + /* >> + * ETE if ARCHVER is 5 (ARCHVER is 4 for ETM) and ARCHPART is 0xA13. >> + * See ETM_DEVARCH_ETE_ARCH in coresight-etm4x.h >> + */ >> + return TRCDEVARCH_ARCHVER(trcdevarch) == 5 && TRCDEVARCH_ARCHPART(trcdevarch) == 0xA13; > > I think this is incorrect. > > Here should check the bit field "REVISION, bits[19:16]". If it's > field value is >= 5, then we can say it supports ETE. I checked the > spec for ETMv4.4 and ETMv4.6, both use the same values for the > Bits[15:12] = 0x4, so the architecture ID is same for ETMv4.x IPs. > I tried to copy this as closely as possible from the ETE driver. See in coresight-etm4x.h #define ETM_DEVARCH_ETE_ARCH \ (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETE | ETM_DEVARCH_PRESENT) Where ETM_DEVARCH_ARCHID_ETE is ARCHVER == 5 and ARCHPART == 0xA13. I didn't check ETM_DEVARCH_ARCHITECT_ARM because I thought that wouldn't be necessary. If we want to make the change do detect >= 5 then I think this should be made in the driver first. @Suzuki, what do you think? Thanks James
On Tue, Aug 03, 2021 at 02:09:38PM +0100, James Clark wrote: [...] > >> -static enum _ocsd_arch_version cs_etm_decoder__get_arch_ver(u32 reg_idr1) > >> +static enum _ocsd_arch_version cs_etm_decoder__get_arch_ver(u32 reg_idr1, u32 reg_devarch) > >> { > >> + /* ETE has to be v9 so set arch version to v8.3+ (ARCH__AA64) */ > >> + if (cs_etm__is_ete(reg_devarch)) > >> + return ARCH_AA64; > >> + > > > > Based on values used in below change, I think we can unify the ETM > > versio number like: > > > > ARCH_V8R3 : REVISION, bits[19:16] is 0x3 > > ARCH_V8R4 : REVISION, bits[19:16] is 0x4 > > ARCH_V8R5 : REVISION, bits[19:16] is 0x5 > > Do you mean make this change in OpenCSD? At the moment it understands these > values so I'm not sure if the extra ones would be useful: Yes. As Mike said, these new macros will cause big changes in OpenCSD, so I don't have strong opinion to add more macros for tracer versions. > >> +struct cs_ete_trace_params { > >> + struct cs_etmv4_trace_params base_params; > >> + u32 reg_devarch; > > > > As we have said, can we directly support ETMv4.5, so that it can > > smoothly support ETE features? If so, we don't need to add a new > > structure "cs_ete_trace_params" at here. > > > > I think with the new magic number change this is more likely to stay, > what are your thoughts? Agreed. Just wander if need to define the struct cs_ete_trace_params as below? struct cs_ete_trace_params { u32 reg_idr0; u32 reg_idr1; u32 reg_idr2; u32 reg_idr8; u32 reg_configr; u32 reg_traceidr; u32 reg_devarch; } > >> + > >> +#define TRCDEVARCH_ARCHPART_SHIFT 0 > >> +#define TRCDEVARCH_ARCHPART_MASK GENMASK(11, 0) > >> +#define TRCDEVARCH_ARCHPART(x) (((x) & TRCDEVARCH_ARCHPART_MASK) >> TRCDEVARCH_ARCHPART_SHIFT) > >> + > >> +#define TRCDEVARCH_ARCHVER_SHIFT 12 > >> +#define TRCDEVARCH_ARCHVER_MASK GENMASK(15, 12) > >> +#define TRCDEVARCH_ARCHVER(x) (((x) & TRCDEVARCH_ARCHVER_MASK) >> TRCDEVARCH_ARCHVER_SHIFT) > >> + > >> +bool cs_etm__is_ete(u32 trcdevarch) > >> +{ > >> + /* > >> + * ETE if ARCHVER is 5 (ARCHVER is 4 for ETM) and ARCHPART is 0xA13. > >> + * See ETM_DEVARCH_ETE_ARCH in coresight-etm4x.h > >> + */ > >> + return TRCDEVARCH_ARCHVER(trcdevarch) == 5 && TRCDEVARCH_ARCHPART(trcdevarch) == 0xA13; > > > > I think this is incorrect. > > > > Here should check the bit field "REVISION, bits[19:16]". If it's > > field value is >= 5, then we can say it supports ETE. I checked the > > spec for ETMv4.4 and ETMv4.6, both use the same values for the > > Bits[15:12] = 0x4, so the architecture ID is same for ETMv4.x IPs. > > > > I tried to copy this as closely as possible from the ETE driver. See in coresight-etm4x.h > > #define ETM_DEVARCH_ETE_ARCH \ > (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETE | ETM_DEVARCH_PRESENT) > > Where ETM_DEVARCH_ARCHID_ETE is ARCHVER == 5 and ARCHPART == 0xA13. I didn't check > ETM_DEVARCH_ARCHITECT_ARM because I thought that wouldn't be necessary. If we want to make > the change do detect >= 5 then I think this should be made in the driver first. @Suzuki, > what do you think? The tracer has two fields: - ARCHID bits[15:12] - REVISION, bits[19:16] For ETE its ARCHID[15:12] is 0x5 and ETMv4.x's ARCHID[15:12] is 0x4. So checking ARCHID[15:12] is the right way to distinguish if the tracer is ETE and creates corresponding decoder for it. When reviewed this patch I assumed we also need to create ETE decoder if ETMv4.x has supported packet extension. As Mike confirmed, all ETMv4.x tracers keep to use existed way to create decoder; so it's not necessary to check REVISION bit field. So please ignore my this comment. Thanks, Leo
diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c index 60147c908425..37bc9d6a7677 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -127,8 +127,12 @@ static int cs_etm_decoder__gen_etmv3_config(struct cs_etm_trace_params *params, #define TRCIDR1_TRCARCHMIN_SHIFT 4 #define TRCIDR1_TRCARCHMIN_MASK GENMASK(7, 4) #define TRCIDR1_TRCARCHMIN(x) (((x) & TRCIDR1_TRCARCHMIN_MASK) >> TRCIDR1_TRCARCHMIN_SHIFT) -static enum _ocsd_arch_version cs_etm_decoder__get_arch_ver(u32 reg_idr1) +static enum _ocsd_arch_version cs_etm_decoder__get_arch_ver(u32 reg_idr1, u32 reg_devarch) { + /* ETE has to be v9 so set arch version to v8.3+ (ARCH__AA64) */ + if (cs_etm__is_ete(reg_devarch)) + return ARCH_AA64; + /* * If the ETM trace minor version is 4 or more then we can assume * the architecture is ARCH_AA64 rather than just V8 @@ -150,7 +154,22 @@ static void cs_etm_decoder__gen_etmv4_config(struct cs_etm_trace_params *params, config->reg_idr11 = 0; config->reg_idr12 = 0; config->reg_idr13 = 0; - config->arch_ver = cs_etm_decoder__get_arch_ver(params->etmv4.reg_idr1); + config->arch_ver = cs_etm_decoder__get_arch_ver(params->etmv4.reg_idr1, 0); + config->core_prof = profile_CortexA; +} + +static void cs_etm_decoder__gen_ete_config(struct cs_etm_trace_params *params, + ocsd_ete_cfg *config) +{ + config->reg_configr = params->ete.base_params.reg_configr; + config->reg_traceidr = params->ete.base_params.reg_traceidr; + config->reg_idr0 = params->ete.base_params.reg_idr0; + config->reg_idr1 = params->ete.base_params.reg_idr1; + config->reg_idr2 = params->ete.base_params.reg_idr2; + config->reg_idr8 = params->ete.base_params.reg_idr8; + config->reg_devarch = params->ete.reg_devarch; + config->arch_ver = cs_etm_decoder__get_arch_ver(params->ete.base_params.reg_idr1, + params->ete.reg_devarch); config->core_prof = profile_CortexA; } @@ -598,6 +617,7 @@ cs_etm_decoder__create_etm_decoder(struct cs_etm_decoder_params *d_params, const char *decoder_name; ocsd_etmv3_cfg config_etmv3; ocsd_etmv4_cfg trace_config_etmv4; + ocsd_ete_cfg trace_config_ete; void *trace_config; u8 csid; @@ -615,6 +635,11 @@ cs_etm_decoder__create_etm_decoder(struct cs_etm_decoder_params *d_params, decoder_name = OCSD_BUILTIN_DCD_ETMV4I; trace_config = &trace_config_etmv4; break; + case CS_ETM_PROTO_ETE: + cs_etm_decoder__gen_ete_config(t_params, &trace_config_ete); + decoder_name = OCSD_BUILTIN_DCD_ETE; + trace_config = &trace_config_ete; + break; default: return -1; } diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h index 11f3391d06f2..9137796fe3c5 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h @@ -37,11 +37,17 @@ struct cs_etmv4_trace_params { u32 reg_traceidr; }; +struct cs_ete_trace_params { + struct cs_etmv4_trace_params base_params; + u32 reg_devarch; +}; + struct cs_etm_trace_params { int protocol; union { struct cs_etmv3_trace_params etmv3; struct cs_etmv4_trace_params etmv4; + struct cs_ete_trace_params ete; }; }; @@ -65,6 +71,7 @@ enum { CS_ETM_PROTO_ETMV4i, CS_ETM_PROTO_ETMV4d, CS_ETM_PROTO_PTM, + CS_ETM_PROTO_ETE }; enum cs_etm_decoder_operation { diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 68978f6707a8..870073bce670 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -460,11 +460,44 @@ static void cs_etm__set_trace_param_etmv4(struct cs_etm_trace_params *t_params, t_params[idx].etmv4.reg_traceidr = metadata[idx][CS_ETMV4_TRCTRACEIDR]; } +static void cs_etm__set_trace_param_ete(struct cs_etm_trace_params *t_params, + struct cs_etm_auxtrace *etm, int idx) +{ + u64 **metadata = etm->metadata; + + t_params[idx].protocol = CS_ETM_PROTO_ETE; + t_params[idx].ete.base_params.reg_idr0 = metadata[idx][CS_ETMV4_TRCIDR0]; + t_params[idx].ete.base_params.reg_idr1 = metadata[idx][CS_ETMV4_TRCIDR1]; + t_params[idx].ete.base_params.reg_idr2 = metadata[idx][CS_ETMV4_TRCIDR2]; + t_params[idx].ete.base_params.reg_idr8 = metadata[idx][CS_ETMV4_TRCIDR8]; + t_params[idx].ete.base_params.reg_configr = metadata[idx][CS_ETMV4_TRCCONFIGR]; + t_params[idx].ete.base_params.reg_traceidr = metadata[idx][CS_ETMV4_TRCTRACEIDR]; + t_params[idx].ete.reg_devarch = metadata[idx][CS_ETE_TRCDEVARCH]; +} + +#define TRCDEVARCH_ARCHPART_SHIFT 0 +#define TRCDEVARCH_ARCHPART_MASK GENMASK(11, 0) +#define TRCDEVARCH_ARCHPART(x) (((x) & TRCDEVARCH_ARCHPART_MASK) >> TRCDEVARCH_ARCHPART_SHIFT) + +#define TRCDEVARCH_ARCHVER_SHIFT 12 +#define TRCDEVARCH_ARCHVER_MASK GENMASK(15, 12) +#define TRCDEVARCH_ARCHVER(x) (((x) & TRCDEVARCH_ARCHVER_MASK) >> TRCDEVARCH_ARCHVER_SHIFT) + +bool cs_etm__is_ete(u32 trcdevarch) +{ + /* + * ETE if ARCHVER is 5 (ARCHVER is 4 for ETM) and ARCHPART is 0xA13. + * See ETM_DEVARCH_ETE_ARCH in coresight-etm4x.h + */ + return TRCDEVARCH_ARCHVER(trcdevarch) == 5 && TRCDEVARCH_ARCHPART(trcdevarch) == 0xA13; +} + + static int cs_etm__init_trace_params(struct cs_etm_trace_params *t_params, struct cs_etm_auxtrace *etm, int decoders_per_cpu) { - int i; + int i, num_params; u32 etmidr; u64 architecture; @@ -477,7 +510,19 @@ static int cs_etm__init_trace_params(struct cs_etm_trace_params *t_params, cs_etm__set_trace_param_etmv3(t_params, etm, i, etmidr); break; case __perf_cs_etmv4_magic: - cs_etm__set_trace_param_etmv4(t_params, etm, i); + /* + * If devarch was saved and shows ETE, initialise ETE decoder. Otherwise + * ETM decoder will still be able to decode a subset of the data. The total + * number of params is number of params saved + common block size for v1, + * see cs_etm_get_metadata(). + */ + num_params = etm->metadata[i][CS_ETM_NR_TRC_PARAMS] + + CS_ETM_COMMON_BLK_MAX_V1; + if (num_params > CS_ETE_TRCDEVARCH && + cs_etm__is_ete(etm->metadata[i][CS_ETE_TRCDEVARCH])) + cs_etm__set_trace_param_ete(t_params, etm, i); + else + cs_etm__set_trace_param_etmv4(t_params, etm, i); break; default: return -EINVAL; diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h index 52d82dce9d59..514083819657 100644 --- a/tools/perf/util/cs-etm.h +++ b/tools/perf/util/cs-etm.h @@ -203,6 +203,7 @@ void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq, u8 trace_chan_id); struct cs_etm_packet_queue *cs_etm__etmq_get_packet_queue(struct cs_etm_queue *etmq, u8 trace_chan_id); +bool cs_etm__is_ete(u32 trcdevarch); #else static inline int cs_etm__process_auxtrace_info(union perf_event *event __maybe_unused,
If the TRCDEVARCH register was saved, and it shows that ETE is present, then instantiate an OCSD_BUILTIN_DCD_ETE decoder instead of OCSD_BUILTIN_DCD_ETMV4I. ETE is the new trace feature for Armv9. Testing performed ================= * Old files with v0 headers still open correctly * Old files with v1 headers with no TRCDEVARCH saved still open * New files with TRCDEVARCH open using an old version of perf that supports v1 headers * Coresight decoding results in the same output if there are no new ETE packet types Signed-off-by: James Clark <james.clark@arm.com> --- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 29 ++++++++++- .../perf/util/cs-etm-decoder/cs-etm-decoder.h | 7 +++ tools/perf/util/cs-etm.c | 49 ++++++++++++++++++- tools/perf/util/cs-etm.h | 1 + 4 files changed, 82 insertions(+), 4 deletions(-)