diff mbox series

[v7,3/4] dt-bindings: pwm: add IPQ6018 binding

Message ID dbf064fb60b1654af25f65d89f75bd397162d701.1629884907.git.baruch@tkos.co.il (mailing list archive)
State Superseded
Headers show
Series [v7,1/4] dt-bindings: mfd: qcom,tcsr: document ipq6018 compatible | expand

Commit Message

Baruch Siach Aug. 25, 2021, 9:48 a.m. UTC
DT binding for the PWM block in Qualcomm IPQ6018 SoC.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
v7:

  Use 'reg' instead of 'offset' (Rob)

  Drop 'clock-names' and 'assigned-clock*' (Bjorn)

  Use single cell address/size in example node (Bjorn)

  Move '#pwm-cells' lower in example node (Bjorn)

  List 'reg' as required

v6:

  Device node is child of TCSR; remove phandle (Rob Herring)

  Add assigned-clocks/assigned-clock-rates (Uwe Kleine-König)

v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn
    Andersson, Kathiravan T)

v4: Update the binding example node as well (Rob Herring's bot)

v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring)

v2: Make #pwm-cells const (Rob Herring)
---
 .../devicetree/bindings/pwm/ipq-pwm.yaml      | 52 +++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml

Comments

Rob Herring Aug. 25, 2021, 2:10 p.m. UTC | #1
On Wed, 25 Aug 2021 12:48:26 +0300, Baruch Siach wrote:
> DT binding for the PWM block in Qualcomm IPQ6018 SoC.
> 
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> ---
> v7:
> 
>   Use 'reg' instead of 'offset' (Rob)
> 
>   Drop 'clock-names' and 'assigned-clock*' (Bjorn)
> 
>   Use single cell address/size in example node (Bjorn)
> 
>   Move '#pwm-cells' lower in example node (Bjorn)
> 
>   List 'reg' as required
> 
> v6:
> 
>   Device node is child of TCSR; remove phandle (Rob Herring)
> 
>   Add assigned-clocks/assigned-clock-rates (Uwe Kleine-König)
> 
> v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn
>     Andersson, Kathiravan T)
> 
> v4: Update the binding example node as well (Rob Herring's bot)
> 
> v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring)
> 
> v2: Make #pwm-cells const (Rob Herring)
> ---
>  .../devicetree/bindings/pwm/ipq-pwm.yaml      | 52 +++++++++++++++++++
>  1 file changed, 52 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/pwm/ipq-pwm.example.dt.yaml:0:0: /example-0/syscon@1937000: failed to match any schema with compatible: ['qcom,tcsr-ipq6018', 'syscon', 'simple-mfd']

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1520591

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.
Baruch Siach Aug. 25, 2021, 2:59 p.m. UTC | #2
Hi Rob,

On Wed, Aug 25 2021, Rob Herring wrote:

> On Wed, 25 Aug 2021 12:48:26 +0300, Baruch Siach wrote:
>> DT binding for the PWM block in Qualcomm IPQ6018 SoC.
>> 
>> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
>> ---
>> v7:
>> 
>>   Use 'reg' instead of 'offset' (Rob)
>> 
>>   Drop 'clock-names' and 'assigned-clock*' (Bjorn)
>> 
>>   Use single cell address/size in example node (Bjorn)
>> 
>>   Move '#pwm-cells' lower in example node (Bjorn)
>> 
>>   List 'reg' as required
>> 
>> v6:
>> 
>>   Device node is child of TCSR; remove phandle (Rob Herring)
>> 
>>   Add assigned-clocks/assigned-clock-rates (Uwe Kleine-König)
>> 
>> v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn
>>     Andersson, Kathiravan T)
>> 
>> v4: Update the binding example node as well (Rob Herring's bot)
>> 
>> v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring)
>> 
>> v2: Make #pwm-cells const (Rob Herring)
>> ---
>>  .../devicetree/bindings/pwm/ipq-pwm.yaml      | 52 +++++++++++++++++++
>>  1 file changed, 52 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> Documentation/devicetree/bindings/pwm/ipq-pwm.example.dt.yaml:0:0:
> /example-0/syscon@1937000: failed to match any schema with compatible:
> ['qcom,tcsr-ipq6018', 'syscon', 'simple-mfd']

What can I do about that? Is it because qcom,tcsr-ipq6018 is documented
in a non-yaml plain .txt file?

Thanks,
baruch

> doc reference errors (make refcheckdocs):
>
> See https://patchwork.ozlabs.org/patch/1520591
>
> This check can fail if there are any dependencies. The base for a patch
> series is generally the most recent rc1.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit.
Rob Herring Aug. 25, 2021, 3:45 p.m. UTC | #3
On Wed, Aug 25, 2021 at 12:48:26PM +0300, Baruch Siach wrote:
> DT binding for the PWM block in Qualcomm IPQ6018 SoC.
> 
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> ---
> v7:
> 
>   Use 'reg' instead of 'offset' (Rob)
> 
>   Drop 'clock-names' and 'assigned-clock*' (Bjorn)
> 
>   Use single cell address/size in example node (Bjorn)
> 
>   Move '#pwm-cells' lower in example node (Bjorn)
> 
>   List 'reg' as required
> 
> v6:
> 
>   Device node is child of TCSR; remove phandle (Rob Herring)
> 
>   Add assigned-clocks/assigned-clock-rates (Uwe Kleine-König)
> 
> v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn
>     Andersson, Kathiravan T)
> 
> v4: Update the binding example node as well (Rob Herring's bot)
> 
> v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring)
> 
> v2: Make #pwm-cells const (Rob Herring)
> ---
>  .../devicetree/bindings/pwm/ipq-pwm.yaml      | 52 +++++++++++++++++++
>  1 file changed, 52 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
> new file mode 100644
> index 000000000000..edfec41e77e5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
> @@ -0,0 +1,52 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm IPQ6018 PWM controller
> +
> +maintainers:
> +  - Baruch Siach <baruch@tkos.co.il>
> +
> +properties:
> +  "#pwm-cells":
> +    const: 2
> +
> +  compatible:
> +    const: qcom,ipq6018-pwm
> +
> +  reg:
> +    description: Offset of PWM register in the TCSR block.
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - "#pwm-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
> +
> +    tcsr: syscon@1937000 {
> +        compatible = "qcom,tcsr-ipq6018", "syscon", "simple-mfd";

This needs to be documented. Some visibility into what else is in this 
block would be nice so we can make some informed decisions as to what 
all this should look like.

> +        reg = <0x01937000 0x21000>;
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +
> +        pwm: pwm@a010 {
> +            compatible = "qcom,ipq6018-pwm";
> +            reg = <0xa010>;

There's not a length associated with the PWM registers.

> +            clocks = <&gcc GCC_ADSS_PWM_CLK>;
> +            assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>;
> +            assigned-clock-rates = <100000000>;
> +            #pwm-cells = <2>;
> +        };
> +    };
> -- 
> 2.32.0
> 
>
Rob Herring Aug. 25, 2021, 4:12 p.m. UTC | #4
On Wed, Aug 25, 2021 at 05:59:45PM +0300, Baruch Siach wrote:
> Hi Rob,
> 
> On Wed, Aug 25 2021, Rob Herring wrote:
> 
> > On Wed, 25 Aug 2021 12:48:26 +0300, Baruch Siach wrote:
> >> DT binding for the PWM block in Qualcomm IPQ6018 SoC.
> >> 
> >> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> >> ---
> >> v7:
> >> 
> >>   Use 'reg' instead of 'offset' (Rob)
> >> 
> >>   Drop 'clock-names' and 'assigned-clock*' (Bjorn)
> >> 
> >>   Use single cell address/size in example node (Bjorn)
> >> 
> >>   Move '#pwm-cells' lower in example node (Bjorn)
> >> 
> >>   List 'reg' as required
> >> 
> >> v6:
> >> 
> >>   Device node is child of TCSR; remove phandle (Rob Herring)
> >> 
> >>   Add assigned-clocks/assigned-clock-rates (Uwe Kleine-König)
> >> 
> >> v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn
> >>     Andersson, Kathiravan T)
> >> 
> >> v4: Update the binding example node as well (Rob Herring's bot)
> >> 
> >> v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring)
> >> 
> >> v2: Make #pwm-cells const (Rob Herring)
> >> ---
> >>  .../devicetree/bindings/pwm/ipq-pwm.yaml      | 52 +++++++++++++++++++
> >>  1 file changed, 52 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
> >
> > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> > on your patch (DT_CHECKER_FLAGS is new in v5.13):
> >
> > yamllint warnings/errors:
> >
> > dtschema/dtc warnings/errors:
> > Documentation/devicetree/bindings/pwm/ipq-pwm.example.dt.yaml:0:0:
> > /example-0/syscon@1937000: failed to match any schema with compatible:
> > ['qcom,tcsr-ipq6018', 'syscon', 'simple-mfd']
> 
> What can I do about that? Is it because qcom,tcsr-ipq6018 is documented
> in a non-yaml plain .txt file?

No, it is not documented at all.

Rob
Rob Herring Aug. 25, 2021, 4:18 p.m. UTC | #5
On Wed, Aug 25, 2021 at 11:12 AM Rob Herring <robh@kernel.org> wrote:
>
> On Wed, Aug 25, 2021 at 05:59:45PM +0300, Baruch Siach wrote:
> > Hi Rob,
> >
> > On Wed, Aug 25 2021, Rob Herring wrote:
> >
> > > On Wed, 25 Aug 2021 12:48:26 +0300, Baruch Siach wrote:
> > >> DT binding for the PWM block in Qualcomm IPQ6018 SoC.
> > >>
> > >> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> > >> ---
> > >> v7:
> > >>
> > >>   Use 'reg' instead of 'offset' (Rob)
> > >>
> > >>   Drop 'clock-names' and 'assigned-clock*' (Bjorn)
> > >>
> > >>   Use single cell address/size in example node (Bjorn)
> > >>
> > >>   Move '#pwm-cells' lower in example node (Bjorn)
> > >>
> > >>   List 'reg' as required
> > >>
> > >> v6:
> > >>
> > >>   Device node is child of TCSR; remove phandle (Rob Herring)
> > >>
> > >>   Add assigned-clocks/assigned-clock-rates (Uwe Kleine-König)
> > >>
> > >> v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn
> > >>     Andersson, Kathiravan T)
> > >>
> > >> v4: Update the binding example node as well (Rob Herring's bot)
> > >>
> > >> v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring)
> > >>
> > >> v2: Make #pwm-cells const (Rob Herring)
> > >> ---
> > >>  .../devicetree/bindings/pwm/ipq-pwm.yaml      | 52 +++++++++++++++++++
> > >>  1 file changed, 52 insertions(+)
> > >>  create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
> > >
> > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> > > on your patch (DT_CHECKER_FLAGS is new in v5.13):
> > >
> > > yamllint warnings/errors:
> > >
> > > dtschema/dtc warnings/errors:
> > > Documentation/devicetree/bindings/pwm/ipq-pwm.example.dt.yaml:0:0:
> > > /example-0/syscon@1937000: failed to match any schema with compatible:
> > > ['qcom,tcsr-ipq6018', 'syscon', 'simple-mfd']
> >
> > What can I do about that? Is it because qcom,tcsr-ipq6018 is documented
> > in a non-yaml plain .txt file?
>
> No, it is not documented at all.

Sorry, I should read patch 1 first... Still, before adding new
features to an MFD, the base MFD should be converted.

Rob
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
new file mode 100644
index 000000000000..edfec41e77e5
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml
@@ -0,0 +1,52 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ6018 PWM controller
+
+maintainers:
+  - Baruch Siach <baruch@tkos.co.il>
+
+properties:
+  "#pwm-cells":
+    const: 2
+
+  compatible:
+    const: qcom,ipq6018-pwm
+
+  reg:
+    description: Offset of PWM register in the TCSR block.
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - "#pwm-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
+
+    tcsr: syscon@1937000 {
+        compatible = "qcom,tcsr-ipq6018", "syscon", "simple-mfd";
+        reg = <0x01937000 0x21000>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        pwm: pwm@a010 {
+            compatible = "qcom,ipq6018-pwm";
+            reg = <0xa010>;
+            clocks = <&gcc GCC_ADSS_PWM_CLK>;
+            assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>;
+            assigned-clock-rates = <100000000>;
+            #pwm-cells = <2>;
+        };
+    };