| Message ID | 20210825165907.34026-6-philipp.tomsich@vrull.eu (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/riscv: Update QEmu for Zb[abcs] 1.0.0 | expand |
On Thu, Aug 26, 2021 at 3:13 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote: > > The Zb[abcs] ratification package does not include the proposed > shift-one instructions. There currently is no clear plan to whether > these (or variants of them) will be ratified as Zbo (or a different > extension) or what the timeframe for such a decision could be. > > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > (no changes since v3) > > Changes in v3: > - Remove shift-one instructions in a separate commit. > > target/riscv/insn32.decode | 8 ---- > target/riscv/insn_trans/trans_rvb.c.inc | 52 ------------------------- > target/riscv/translate.c | 14 ------- > 3 files changed, 74 deletions(-) > > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 9abdbcb799..7e38477553 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -692,8 +692,6 @@ bset 0010100 .......... 001 ..... 0110011 @r > bclr 0100100 .......... 001 ..... 0110011 @r > binv 0110100 .......... 001 ..... 0110011 @r > bext 0100100 .......... 101 ..... 0110011 @r > -slo 0010000 .......... 001 ..... 0110011 @r > -sro 0010000 .......... 101 ..... 0110011 @r > ror 0110000 .......... 101 ..... 0110011 @r > rol 0110000 .......... 001 ..... 0110011 @r > grev 0110100 .......... 101 ..... 0110011 @r > @@ -703,8 +701,6 @@ bseti 00101. ........... 001 ..... 0010011 @sh > bclri 01001. ........... 001 ..... 0010011 @sh > binvi 01101. ........... 001 ..... 0010011 @sh > bexti 01001. ........... 101 ..... 0010011 @sh > -sloi 00100. ........... 001 ..... 0010011 @sh > -sroi 00100. ........... 101 ..... 0010011 @sh > rori 01100. ........... 101 ..... 0010011 @sh > grevi 01101. ........... 101 ..... 0010011 @sh > gorci 00101. ........... 101 ..... 0010011 @sh > @@ -716,15 +712,11 @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 > > packw 0000100 .......... 100 ..... 0111011 @r > packuw 0100100 .......... 100 ..... 0111011 @r > -slow 0010000 .......... 001 ..... 0111011 @r > -srow 0010000 .......... 101 ..... 0111011 @r > rorw 0110000 .......... 101 ..... 0111011 @r > rolw 0110000 .......... 001 ..... 0111011 @r > grevw 0110100 .......... 101 ..... 0111011 @r > gorcw 0010100 .......... 101 ..... 0111011 @r > > -sloiw 0010000 .......... 001 ..... 0011011 @sh5 > -sroiw 0010000 .......... 101 ..... 0011011 @sh5 > roriw 0110000 .......... 101 ..... 0011011 @sh5 > greviw 0110100 .......... 101 ..... 0011011 @sh5 > gorciw 0010100 .......... 101 ..... 0011011 @sh5 > diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc > index 975492d45c..ac706349f5 100644 > --- a/target/riscv/insn_trans/trans_rvb.c.inc > +++ b/target/riscv/insn_trans/trans_rvb.c.inc > @@ -162,30 +162,6 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a) > return gen_shifti(ctx, a, gen_bext); > } > > -static bool trans_slo(DisasContext *ctx, arg_slo *a) > -{ > - REQUIRE_EXT(ctx, RVB); > - return gen_shift(ctx, a, gen_slo); > -} > - > -static bool trans_sloi(DisasContext *ctx, arg_sloi *a) > -{ > - REQUIRE_EXT(ctx, RVB); > - return gen_shifti(ctx, a, gen_slo); > -} > - > -static bool trans_sro(DisasContext *ctx, arg_sro *a) > -{ > - REQUIRE_EXT(ctx, RVB); > - return gen_shift(ctx, a, gen_sro); > -} > - > -static bool trans_sroi(DisasContext *ctx, arg_sroi *a) > -{ > - REQUIRE_EXT(ctx, RVB); > - return gen_shifti(ctx, a, gen_sro); > -} > - > static bool trans_ror(DisasContext *ctx, arg_ror *a) > { > REQUIRE_EXT(ctx, RVB); > @@ -279,34 +255,6 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a) > return gen_arith(ctx, a, gen_packuw); > } > > -static bool trans_slow(DisasContext *ctx, arg_slow *a) > -{ > - REQUIRE_64BIT(ctx); > - REQUIRE_EXT(ctx, RVB); > - return gen_shiftw(ctx, a, gen_slo); > -} > - > -static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a) > -{ > - REQUIRE_64BIT(ctx); > - REQUIRE_EXT(ctx, RVB); > - return gen_shiftiw(ctx, a, gen_slo); > -} > - > -static bool trans_srow(DisasContext *ctx, arg_srow *a) > -{ > - REQUIRE_64BIT(ctx); > - REQUIRE_EXT(ctx, RVB); > - return gen_shiftw(ctx, a, gen_sro); > -} > - > -static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) > -{ > - REQUIRE_64BIT(ctx); > - REQUIRE_EXT(ctx, RVB); > - return gen_shiftiw(ctx, a, gen_sro); > -} > - > static bool trans_rorw(DisasContext *ctx, arg_rorw *a) > { > REQUIRE_64BIT(ctx); > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 6983be5723..fc22ae82d0 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -595,20 +595,6 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt) > tcg_gen_andi_tl(ret, ret, 1); > } > > -static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2) > -{ > - tcg_gen_not_tl(ret, arg1); > - tcg_gen_shl_tl(ret, ret, arg2); > - tcg_gen_not_tl(ret, ret); > -} > - > -static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) > -{ > - tcg_gen_not_tl(ret, arg1); > - tcg_gen_shr_tl(ret, ret, arg2); > - tcg_gen_not_tl(ret, ret); > -} > - > static bool gen_grevi(DisasContext *ctx, arg_grevi *a) > { > TCGv source1 = tcg_temp_new(); > -- > 2.25.1 > >
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 9abdbcb799..7e38477553 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -692,8 +692,6 @@ bset 0010100 .......... 001 ..... 0110011 @r bclr 0100100 .......... 001 ..... 0110011 @r binv 0110100 .......... 001 ..... 0110011 @r bext 0100100 .......... 101 ..... 0110011 @r -slo 0010000 .......... 001 ..... 0110011 @r -sro 0010000 .......... 101 ..... 0110011 @r ror 0110000 .......... 101 ..... 0110011 @r rol 0110000 .......... 001 ..... 0110011 @r grev 0110100 .......... 101 ..... 0110011 @r @@ -703,8 +701,6 @@ bseti 00101. ........... 001 ..... 0010011 @sh bclri 01001. ........... 001 ..... 0010011 @sh binvi 01101. ........... 001 ..... 0010011 @sh bexti 01001. ........... 101 ..... 0010011 @sh -sloi 00100. ........... 001 ..... 0010011 @sh -sroi 00100. ........... 101 ..... 0010011 @sh rori 01100. ........... 101 ..... 0010011 @sh grevi 01101. ........... 101 ..... 0010011 @sh gorci 00101. ........... 101 ..... 0010011 @sh @@ -716,15 +712,11 @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 packw 0000100 .......... 100 ..... 0111011 @r packuw 0100100 .......... 100 ..... 0111011 @r -slow 0010000 .......... 001 ..... 0111011 @r -srow 0010000 .......... 101 ..... 0111011 @r rorw 0110000 .......... 101 ..... 0111011 @r rolw 0110000 .......... 001 ..... 0111011 @r grevw 0110100 .......... 101 ..... 0111011 @r gorcw 0010100 .......... 101 ..... 0111011 @r -sloiw 0010000 .......... 001 ..... 0011011 @sh5 -sroiw 0010000 .......... 101 ..... 0011011 @sh5 roriw 0110000 .......... 101 ..... 0011011 @sh5 greviw 0110100 .......... 101 ..... 0011011 @sh5 gorciw 0010100 .......... 101 ..... 0011011 @sh5 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 975492d45c..ac706349f5 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -162,30 +162,6 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a) return gen_shifti(ctx, a, gen_bext); } -static bool trans_slo(DisasContext *ctx, arg_slo *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, gen_slo); -} - -static bool trans_sloi(DisasContext *ctx, arg_sloi *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shifti(ctx, a, gen_slo); -} - -static bool trans_sro(DisasContext *ctx, arg_sro *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, gen_sro); -} - -static bool trans_sroi(DisasContext *ctx, arg_sroi *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shifti(ctx, a, gen_sro); -} - static bool trans_ror(DisasContext *ctx, arg_ror *a) { REQUIRE_EXT(ctx, RVB); @@ -279,34 +255,6 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a) return gen_arith(ctx, a, gen_packuw); } -static bool trans_slow(DisasContext *ctx, arg_slow *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_slo); -} - -static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftiw(ctx, a, gen_slo); -} - -static bool trans_srow(DisasContext *ctx, arg_srow *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_sro); -} - -static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftiw(ctx, a, gen_sro); -} - static bool trans_rorw(DisasContext *ctx, arg_rorw *a) { REQUIRE_64BIT(ctx); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6983be5723..fc22ae82d0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -595,20 +595,6 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt) tcg_gen_andi_tl(ret, ret, 1); } -static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_not_tl(ret, arg1); - tcg_gen_shl_tl(ret, ret, arg2); - tcg_gen_not_tl(ret, ret); -} - -static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_not_tl(ret, arg1); - tcg_gen_shr_tl(ret, ret, arg2); - tcg_gen_not_tl(ret, ret); -} - static bool gen_grevi(DisasContext *ctx, arg_grevi *a) { TCGv source1 = tcg_temp_new();