[13/40] mfd: ti_am335x_tscadc: Reword the comment explaining the dividers

Commit Message

Miquel Raynal Aug. 25, 2021, 3:24 p.m. UTC

The comment misses the main information which is that we assume that a
sample takes 15 ADC clock cycles to be generated. Let's take the
occasion to rework a little bit this comment.

Signed-off-by: Miquel Raynal <[e-mail]>
---
 drivers/mfd/ti_am335x_tscadc.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Comments

Jonathan Cameron Aug. 30, 2021, 1:43 p.m. UTC | #1

On Wed, 25 Aug 2021 17:24:51 +0200
Miquel Raynal <[e-mail]> wrote:

> The comment misses the main information which is that we assume that a
> sample takes 15 ADC clock cycles to be generated. Let's take the
> occasion to rework a little bit this comment.
> 
> Signed-off-by: Miquel Raynal <[e-mail]>
Fair enough. It does seem a little clearer to me after your rewording.

Reviewed-by: Jonathan Cameron <[e-mail]>

> ---
>  drivers/mfd/ti_am335x_tscadc.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/mfd/ti_am335x_tscadc.c b/drivers/mfd/ti_am335x_tscadc.c
> index 0fef35e1e64b..3afe22680973 100644
> --- a/drivers/mfd/ti_am335x_tscadc.c
> +++ b/drivers/mfd/ti_am335x_tscadc.c
> @@ -195,12 +195,12 @@ static	int ti_tscadc_probe(struct platform_device *pdev)
>  	pm_runtime_get_sync(&pdev->dev);
>  
>  	/*
> -	 * The TSC_ADC_Subsystem has 2 clock domains
> -	 * OCP_CLK and ADC_CLK.
> -	 * The ADC clock is expected to run at target of 3MHz,
> -	 * and expected to capture 12-bit data at a rate of 200 KSPS.
> -	 * The TSC_ADC_SS controller design assumes the OCP clock is
> -	 * at least 6x faster than the ADC clock.
> +	 * The TSC_ADC_Subsystem has 2 clock domains: OCP_CLK and ADC_CLK.
> +	 * ADCs produce a 12-bit sample every 15 ADC_CLK cycles.
> +	 * am33xx ADCs expect to capture 200ksps.
> +	 * We need the ADC clocks to run at 3MHz.
> +	 * This frequency is valid since TSC_ADC_SS controller design
> +	 * assumes the OCP clock is at least 6x faster than the ADC clock.
>  	 */
>  	clk = devm_clk_get(&pdev->dev, "adc_tsc_fck");
>  	if (IS_ERR(clk)) {

Patch

diff --git a/drivers/mfd/ti_am335x_tscadc.c b/drivers/mfd/ti_am335x_tscadc.c
index 0fef35e1e64b..3afe22680973 100644
--- a/drivers/mfd/ti_am335x_tscadc.c
+++ b/drivers/mfd/ti_am335x_tscadc.c
@@ -195,12 +195,12 @@  static	int ti_tscadc_probe(struct platform_device *pdev)
 	pm_runtime_get_sync(&pdev->dev);
 
 	/*
-	 * The TSC_ADC_Subsystem has 2 clock domains
-	 * OCP_CLK and ADC_CLK.
-	 * The ADC clock is expected to run at target of 3MHz,
-	 * and expected to capture 12-bit data at a rate of 200 KSPS.
-	 * The TSC_ADC_SS controller design assumes the OCP clock is
-	 * at least 6x faster than the ADC clock.
+	 * The TSC_ADC_Subsystem has 2 clock domains: OCP_CLK and ADC_CLK.
+	 * ADCs produce a 12-bit sample every 15 ADC_CLK cycles.
+	 * am33xx ADCs expect to capture 200ksps.
+	 * We need the ADC clocks to run at 3MHz.
+	 * This frequency is valid since TSC_ADC_SS controller design
+	 * assumes the OCP clock is at least 6x faster than the ADC clock.
 	 */
 	clk = devm_clk_get(&pdev->dev, "adc_tsc_fck");
 	if (IS_ERR(clk)) {