diff mbox series

[v2,28/46] mfd: ti_am335x_tscadc: Add TSC prefix in certain macros

Message ID 20210902215144.507243-29-miquel.raynal@bootlin.com (mailing list archive)
State New, archived
Headers show
Series TI AM437X ADC1 | expand

Commit Message

Miquel Raynal Sept. 2, 2021, 9:51 p.m. UTC 
While the register list (and names) between ADC0 and ADC1 are pretty
close, the bits inside changed a little bit. To avoid any future
confusion, let's add the TSC prefix when some bits are in a register
that is common to both revisions of the ADC, but are specific to the
am33xx hardware.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 drivers/mfd/ti_am335x_tscadc.c       | 10 +++++-----
 include/linux/mfd/ti_am335x_tscadc.h | 16 ++++++++--------
 2 files changed, 13 insertions(+), 13 deletions(-)

Comments

Jonathan Cameron Sept. 5, 2021, 1:15 p.m. UTC | #1 
On Thu,  2 Sep 2021 23:51:26 +0200
Miquel Raynal <miquel.raynal@bootlin.com> wrote:

> While the register list (and names) between ADC0 and ADC1 are pretty
> close, the bits inside changed a little bit. To avoid any future
> confusion, let's add the TSC prefix when some bits are in a register
> that is common to both revisions of the ADC, but are specific to the
> am33xx hardware.
> 
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Given all I suggested last time was things you've done in earlier patches now
this LGTM

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> ---
>  drivers/mfd/ti_am335x_tscadc.c       | 10 +++++-----
>  include/linux/mfd/ti_am335x_tscadc.h | 16 ++++++++--------
>  2 files changed, 13 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/mfd/ti_am335x_tscadc.c b/drivers/mfd/ti_am335x_tscadc.c
> index eba5fba8cf78..2fdee0f4814f 100644
> --- a/drivers/mfd/ti_am335x_tscadc.c
> +++ b/drivers/mfd/ti_am335x_tscadc.c
> @@ -220,13 +220,13 @@ static	int ti_tscadc_probe(struct platform_device *pdev)
>  	regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div);
>  
>  	/* Set the control register bits */
> -	tscadc->ctrl = CNTRLREG_STEPCONFIGWRT | CNTRLREG_STEPID;
> +	tscadc->ctrl = CNTRLREG_TSC_STEPCONFIGWRT | CNTRLREG_STEPID;
>  	if (tsc_wires > 0) {
> -		tscadc->ctrl |= CNTRLREG_TSCENB;
> +		tscadc->ctrl |= CNTRLREG_TSC_ENB;
>  		if (tsc_wires == 5)
> -			tscadc->ctrl |= CNTRLREG_5WIRE;
> +			tscadc->ctrl |= CNTRLREG_TSC_5WIRE;
>  		else
> -			tscadc->ctrl |= CNTRLREG_4WIRE;
> +			tscadc->ctrl |= CNTRLREG_TSC_4WIRE;
>  	}
>  	regmap_write(tscadc->regmap, REG_CTRL, tscadc->ctrl);
>  
> @@ -326,7 +326,7 @@ static const struct ti_tscadc_data tscdata = {
>  	.compat_tscmag = "ti,am3359-tsc",
>  	.name_adc = "TI-am335x-adc",
>  	.compat_adc = "ti,am3359-adc",
> -	.target_clk_rate = ADC_CLK,
> +	.target_clk_rate = TSC_ADC_CLK,
>  };
>  
>  static const struct of_device_id ti_tscadc_dt_ids[] = {
> diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h
> index 271b5aefc474..29d3195b0193 100644
> --- a/include/linux/mfd/ti_am335x_tscadc.h
> +++ b/include/linux/mfd/ti_am335x_tscadc.h
> @@ -113,14 +113,14 @@
>  /* Control register */
>  #define CNTRLREG_SSENB		BIT(0)
>  #define CNTRLREG_STEPID		BIT(1)
> -#define CNTRLREG_STEPCONFIGWRT	BIT(2)
> +#define CNTRLREG_TSC_STEPCONFIGWRT BIT(2)
>  #define CNTRLREG_POWERDOWN	BIT(4)
> -#define CNTRLREG_AFE_CTRL_MASK	GENMASK(6, 5)
> -#define CNTRLREG_AFE_CTRL(val)	FIELD_PREP(CNTRLREG_AFE_CTRL_MASK, (val))
> -#define CNTRLREG_4WIRE		CNTRLREG_AFE_CTRL(1)
> -#define CNTRLREG_5WIRE		CNTRLREG_AFE_CTRL(2)
> -#define CNTRLREG_8WIRE		CNTRLREG_AFE_CTRL(3)
> -#define CNTRLREG_TSCENB		BIT(7)
> +#define CNTRLREG_TSC_AFE_CTRL_MASK GENMASK(6, 5)
> +#define CNTRLREG_TSC_AFE_CTRL(val) FIELD_PREP(CNTRLREG_TSC_AFE_CTRL_MASK, (val))
> +#define CNTRLREG_TSC_4WIRE	CNTRLREG_TSC_AFE_CTRL(1)
> +#define CNTRLREG_TSC_5WIRE	CNTRLREG_TSC_AFE_CTRL(2)
> +#define CNTRLREG_TSC_8WIRE	CNTRLREG_TSC_AFE_CTRL(3)
> +#define CNTRLREG_TSC_ENB	BIT(7)
>  
>  /* FIFO READ Register */
>  #define FIFOREAD_DATA_MASK	GENMASK(11, 0)
> @@ -134,7 +134,7 @@
>  #define SEQ_STATUS		BIT(5)
>  #define CHARGE_STEP		0x11
>  
> -#define ADC_CLK			3000000
> +#define TSC_ADC_CLK		3000000
>  #define TOTAL_STEPS		16
>  #define TOTAL_CHANNELS		8
>  #define FIFO1_THRESHOLD		19
diff mbox series

Patch

diff --git a/drivers/mfd/ti_am335x_tscadc.c b/drivers/mfd/ti_am335x_tscadc.c
index eba5fba8cf78..2fdee0f4814f 100644
--- a/drivers/mfd/ti_am335x_tscadc.c
+++ b/drivers/mfd/ti_am335x_tscadc.c
@@ -220,13 +220,13 @@  static	int ti_tscadc_probe(struct platform_device *pdev)
 	regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div);
 
 	/* Set the control register bits */
-	tscadc->ctrl = CNTRLREG_STEPCONFIGWRT | CNTRLREG_STEPID;
+	tscadc->ctrl = CNTRLREG_TSC_STEPCONFIGWRT | CNTRLREG_STEPID;
 	if (tsc_wires > 0) {
-		tscadc->ctrl |= CNTRLREG_TSCENB;
+		tscadc->ctrl |= CNTRLREG_TSC_ENB;
 		if (tsc_wires == 5)
-			tscadc->ctrl |= CNTRLREG_5WIRE;
+			tscadc->ctrl |= CNTRLREG_TSC_5WIRE;
 		else
-			tscadc->ctrl |= CNTRLREG_4WIRE;
+			tscadc->ctrl |= CNTRLREG_TSC_4WIRE;
 	}
 	regmap_write(tscadc->regmap, REG_CTRL, tscadc->ctrl);
 
@@ -326,7 +326,7 @@  static const struct ti_tscadc_data tscdata = {
 	.compat_tscmag = "ti,am3359-tsc",
 	.name_adc = "TI-am335x-adc",
 	.compat_adc = "ti,am3359-adc",
-	.target_clk_rate = ADC_CLK,
+	.target_clk_rate = TSC_ADC_CLK,
 };
 
 static const struct of_device_id ti_tscadc_dt_ids[] = {
diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h
index 271b5aefc474..29d3195b0193 100644
--- a/include/linux/mfd/ti_am335x_tscadc.h
+++ b/include/linux/mfd/ti_am335x_tscadc.h
@@ -113,14 +113,14 @@ 
 /* Control register */
 #define CNTRLREG_SSENB		BIT(0)
 #define CNTRLREG_STEPID		BIT(1)
-#define CNTRLREG_STEPCONFIGWRT	BIT(2)
+#define CNTRLREG_TSC_STEPCONFIGWRT BIT(2)
 #define CNTRLREG_POWERDOWN	BIT(4)
-#define CNTRLREG_AFE_CTRL_MASK	GENMASK(6, 5)
-#define CNTRLREG_AFE_CTRL(val)	FIELD_PREP(CNTRLREG_AFE_CTRL_MASK, (val))
-#define CNTRLREG_4WIRE		CNTRLREG_AFE_CTRL(1)
-#define CNTRLREG_5WIRE		CNTRLREG_AFE_CTRL(2)
-#define CNTRLREG_8WIRE		CNTRLREG_AFE_CTRL(3)
-#define CNTRLREG_TSCENB		BIT(7)
+#define CNTRLREG_TSC_AFE_CTRL_MASK GENMASK(6, 5)
+#define CNTRLREG_TSC_AFE_CTRL(val) FIELD_PREP(CNTRLREG_TSC_AFE_CTRL_MASK, (val))
+#define CNTRLREG_TSC_4WIRE	CNTRLREG_TSC_AFE_CTRL(1)
+#define CNTRLREG_TSC_5WIRE	CNTRLREG_TSC_AFE_CTRL(2)
+#define CNTRLREG_TSC_8WIRE	CNTRLREG_TSC_AFE_CTRL(3)
+#define CNTRLREG_TSC_ENB	BIT(7)
 
 /* FIFO READ Register */
 #define FIFOREAD_DATA_MASK	GENMASK(11, 0)
@@ -134,7 +134,7 @@ 
 #define SEQ_STATUS		BIT(5)
 #define CHARGE_STEP		0x11
 
-#define ADC_CLK			3000000
+#define TSC_ADC_CLK		3000000
 #define TOTAL_STEPS		16
 #define TOTAL_CHANNELS		8
 #define FIFO1_THRESHOLD		19