| Message ID | 239f7624f3ac3793993dc045d451079aa555b90d.1630929059.git.jane.malalane@citrix.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | x86/cpuid: Use AMD's NullSelectorClearsBase CPUID bit | expand |
On 06.09.2021 14:00, Jane Malalane wrote: > AMD Zen3 adds the NullSelectorClearsBase bit to indicate that loading > a NULL segment selector zeroes the base and limit fields, as well as > just attributes. > > Expose bit to all guests. > > Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com> > Signed-off-by: Jane Malalane <jane.malalane@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com>
On 06/09/2021 13:00, Jane Malalane wrote: > diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h > index 380b51b1b3..e5a7c94c78 100644 > --- a/xen/include/public/arch-x86/cpufeatureset.h > +++ b/xen/include/public/arch-x86/cpufeatureset.h > @@ -285,6 +285,7 @@ XEN_CPUFEATURE(FSRCS, 10*32+12) /*A Fast Short REP CMPSB/SCASB */ > > /* AMD-defined CPU features, CPUID level 0x80000021.eax, word 11 */ > XEN_CPUFEATURE(LFENCE_DISPATCH, 11*32+ 2) /*A LFENCE always serializing */ > +XEN_CPUFEATURE(NSCB, 11*32+ 6) /*A Null Selector Clears Base */ On second thoughts, I'm tempted to add " (and limit too)" to the comment. Can be fixed on commit. ~Andrew
diff --git a/tools/libs/light/libxl_cpuid.c b/tools/libs/light/libxl_cpuid.c index b2c673841a..d667c36f31 100644 --- a/tools/libs/light/libxl_cpuid.c +++ b/tools/libs/light/libxl_cpuid.c @@ -289,6 +289,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str) {"svm_pausefilt",0x8000000a, NA, CPUID_REG_EDX, 10, 1}, {"lfence+", 0x80000021, NA, CPUID_REG_EAX, 2, 1}, + {"nscb", 0x80000021, NA, CPUID_REG_EAX, 6, 1}, {"maxhvleaf", 0x40000000, NA, CPUID_REG_EAX, 0, 8}, diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c index 735bcf8f0e..d79e67ecfb 100644 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -185,6 +185,7 @@ static const char *const str_7a1[32] = static const char *const str_e21a[32] = { [ 2] = "lfence+", + [ 6] = "nscb", }; static const struct { diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 380b51b1b3..e5a7c94c78 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -285,6 +285,7 @@ XEN_CPUFEATURE(FSRCS, 10*32+12) /*A Fast Short REP CMPSB/SCASB */ /* AMD-defined CPU features, CPUID level 0x80000021.eax, word 11 */ XEN_CPUFEATURE(LFENCE_DISPATCH, 11*32+ 2) /*A LFENCE always serializing */ +XEN_CPUFEATURE(NSCB, 11*32+ 6) /*A Null Selector Clears Base */ #endif /* XEN_CPUFEATURE */
AMD Zen3 adds the NullSelectorClearsBase bit to indicate that loading a NULL segment selector zeroes the base and limit fields, as well as just attributes. Expose bit to all guests. Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com> Signed-off-by: Jane Malalane <jane.malalane@citrix.com> --- CC: Wei Liu <wl@xen.org> CC: Jan Beulich <jbeulich@suse.com> CC: Andrew Cooper <andrew.cooper3@citrix.com> CC: "Roger Pau Monné" <roger.pau@citrix.com> CC: Pu Wen <puwen@hygon.cn> CC: Andy Lutomirski <luto@kernel.org> --- tools/libs/light/libxl_cpuid.c | 1 + tools/misc/xen-cpuid.c | 1 + xen/include/public/arch-x86/cpufeatureset.h | 1 + 3 files changed, 3 insertions(+)