| Message ID | 20210903231536.225540-3-frattaroli.nicolas@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Rockchip I2S/TDM controller | expand |
On Sat, 04 Sep 2021 01:15:34 +0200, Nicolas Frattaroli wrote: > This adds the YAML bindings for the Rockchip I2S/TDM audio driver. > > Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> > --- > .../bindings/sound/rockchip,i2s-tdm.yaml | 218 ++++++++++++++++++ > MAINTAINERS | 1 + > 2 files changed, 219 insertions(+) > create mode 100644 Documentation/devicetree/bindings/sound/rockchip,i2s-tdm.yaml > Reviewed-by: Rob Herring <robh@kernel.org>
On Sat, Sep 04, 2021 at 01:15:34AM +0200, Nicolas Frattaroli wrote: > + rockchip,frame-width: > + $ref: /schemas/types.yaml#/definitions/uint32 > + default: 64 > + minimum: 32 > + maximum: 512 > + description: > + Width of a frame, usually slot width multiplied by number of slots. > + Must be even. Why is this in the binding? This is normally configured by the machine driver setting the TDM slots, not through DT. > + rockchip,mclk-calibrate: > + description: > + Switch between two root clocks depending on the audio sample rate. > + For integer multiples of 8000 (e.g. 48000 Hz), mclk_root0 is used. > + For integer multiples of 11025 (e.g. 44100 Hz), mclk_root1 is used. > + type: boolean Why would we not want to do this, and assuming it's to do with availability can't we detect it simply through seeing if both MCLKs are available? > + rockchip,tdm-fsync-half-frame: > + description: Whether to use half frame fsync. > + type: boolean > + Why is this not part of the normal bus format configuration? I don't know what this is but it sounds a lot like I2S mode...
On Mittwoch, 15. September 2021 16:10:12 CEST Mark Brown wrote: > On Sat, Sep 04, 2021 at 01:15:34AM +0200, Nicolas Frattaroli wrote: > > + rockchip,tdm-fsync-half-frame: > > + description: Whether to use half frame fsync. > > + type: boolean > > + > > Why is this not part of the normal bus format configuration? I don't > know what this is but it sounds a lot like I2S mode... This affects all TDM I2S modes, i.e. TDM Normal, TDM Left Justified and TDM Right Justified. Without tdm-fsync-half-frame, we purportedly get the following output in TDM Normal Mode (I2S Format): (ch0l = channel 0 left, ch0r = channel 0 right) fsync: _____________________________ \____________________________ sdi/sdo: ch0l, ch0r, ..., ch3l, ch3r, ch0l, ch0r, ... With tdm-fsync-half-frame, we purportedly get the following: fsync: _____________________________ \____________________________ sdi/sdo: ch0l, ch1l, ch2l, ch3l, ch0r, ch1r, ch2r, ch3r At least, according to the TRM. I do not have an oscilloscope to verify this myself, and in the following paragraphs, I will elaborate why this seems confusing to me. The comment block "DAI hardware signal polarity" in soc-dai.h seems to imply that what the TRM says the tdm-fsync-half-frame mode is (if one inverts fsync polarity of those waveforms), is what is expected: > * FSYNC "normal" polarity depends on the frame format: > * - I2S: frame consists of left then right channel data. Left channel starts > * with falling FSYNC edge, right channel starts with rising FSYNC edge. > * - Left/Right Justified: frame consists of left then right channel data. > * Left channel starts with rising FSYNC edge, right channel starts with > * falling FSYNC edge. I don't know if this is only applicable to non-TDM I2S, and whether it's normal to have the channels interleaved like that in TDM. I don't see any DAIFMT that does what this does in any case. So to answer the question, it's not part of the bus format because it applies to three bus formats, and I'm completely out of my depth here and wouldn't define three separate bus formats based on my own speculation of how this works.
On Wed, Sep 15, 2021 at 07:06:14PM +0200, Nicolas Frattaroli wrote: > On Mittwoch, 15. September 2021 16:10:12 CEST Mark Brown wrote: > > Why is this not part of the normal bus format configuration? I don't > > know what this is but it sounds a lot like I2S mode... > This affects all TDM I2S modes, i.e. TDM Normal, TDM Left Justified and TDM > Right Justified. > Without tdm-fsync-half-frame, we purportedly get the following output in TDM > Normal Mode (I2S Format): > (ch0l = channel 0 left, ch0r = channel 0 right) > fsync: _____________________________ > \____________________________ > sdi/sdo: ch0l, ch0r, ..., ch3l, ch3r, ch0l, ch0r, ... > > With tdm-fsync-half-frame, we purportedly get the following: > > fsync: _____________________________ > \____________________________ > sdi/sdo: ch0l, ch1l, ch2l, ch3l, ch0r, ch1r, ch2r, ch3r > At least, according to the TRM. I do not have an oscilloscope to verify this > myself, and in the following paragraphs, I will elaborate why this seems > confusing to me. fsync-half-frame is just normal TDM for I2S, the default mode is how DSP mode normally operates. I don't know that there's any pressing need to support mix'n'match here, you could but it should be through the TDM configuration API. > So to answer the question, it's not part of the bus format because it applies > to three bus formats, and I'm completely out of my depth here and wouldn't > define three separate bus formats based on my own speculation of how this > works. It is part of the bus format really. I suspect the hardware is the kind that only really implements DSP mode and can just fake up a LRCLK for I2S in order to interoperate.
On Donnerstag, 16. September 2021 14:25:49 CEST Mark Brown wrote: > On Wed, Sep 15, 2021 at 07:06:14PM +0200, Nicolas Frattaroli wrote: > > On Mittwoch, 15. September 2021 16:10:12 CEST Mark Brown wrote: > > > Why is this not part of the normal bus format configuration? I don't > > > know what this is but it sounds a lot like I2S mode... > > > > This affects all TDM I2S modes, i.e. TDM Normal, TDM Left Justified and > > TDM > > Right Justified. > > > > Without tdm-fsync-half-frame, we purportedly get the following output in > > TDM Normal Mode (I2S Format): > > (ch0l = channel 0 left, ch0r = channel 0 right) > > > > fsync: _____________________________ > > > > \____________________________ > > > > sdi/sdo: ch0l, ch0r, ..., ch3l, ch3r, ch0l, ch0r, ... > > > > With tdm-fsync-half-frame, we purportedly get the following: > > > > fsync: _____________________________ > > > > \____________________________ > > > > sdi/sdo: ch0l, ch1l, ch2l, ch3l, ch0r, ch1r, ch2r, ch3r > > > > At least, according to the TRM. I do not have an oscilloscope to verify > > this myself, and in the following paragraphs, I will elaborate why this > > seems confusing to me. > > fsync-half-frame is just normal TDM for I2S, the default mode is how DSP > mode normally operates. I don't know that there's any pressing need to > support mix'n'match here, you could but it should be through the TDM > configuration API. > > > So to answer the question, it's not part of the bus format because it > > applies to three bus formats, and I'm completely out of my depth here and > > wouldn't define three separate bus formats based on my own speculation of > > how this works. > > It is part of the bus format really. I suspect the hardware is the kind > that only really implements DSP mode and can just fake up a LRCLK for > I2S in order to interoperate. Thank you for your explanation! Going forward, what would be a solution that is acceptable for upstream? As far as I understand, the obvious route here is to drop the rockchip,fsync- half-frame property and just always set this mode when we're using a TDM bus format. Is this correct? According to the TRM, the register bit this sets only affects TDM modes. Though since TDM is not standardised in any way from what I've read online, it is possible that there is hardware out there which expects the non-fsync-half- frame mode, but I am completely fine with only thinking about this hardware when it actually surfaces. Regards, Nicolas Frattaroli
On Sun, Sep 19, 2021 at 07:38:47PM +0200, Nicolas Frattaroli wrote: > Going forward, what would be a solution that is acceptable for upstream? As > far as I understand, the obvious route here is to drop the rockchip,fsync- > half-frame property and just always set this mode when we're using a TDM bus > format. Is this correct? Yes. > According to the TRM, the register bit this sets only affects TDM modes. > Though since TDM is not standardised in any way from what I've read online, it > is possible that there is hardware out there which expects the non-fsync-half- > frame mode, but I am completely fine with only thinking about this hardware > when it actually surfaces. Right, we can figure it out later.
diff --git a/Documentation/devicetree/bindings/sound/rockchip,i2s-tdm.yaml b/Documentation/devicetree/bindings/sound/rockchip,i2s-tdm.yaml new file mode 100644 index 000000000000..a04267ccb0f6 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/rockchip,i2s-tdm.yaml @@ -0,0 +1,218 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/rockchip,i2s-tdm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip I2S/TDM Controller + +description: + The Rockchip I2S/TDM Controller is a Time Division Multiplexed + audio interface found in various Rockchip SoCs, allowing up + to 8 channels of audio over a serial interface. + +maintainers: + - Nicolas Frattaroli <frattaroli.nicolas@gmail.com> + +properties: + compatible: + enum: + - rockchip,px30-i2s-tdm + - rockchip,rk1808-i2s-tdm + - rockchip,rk3308-i2s-tdm + - rockchip,rk3568-i2s-tdm + - rockchip,rv1126-i2s-tdm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + dmas: + minItems: 1 + maxItems: 2 + + dma-names: + minItems: 1 + maxItems: 2 + items: + enum: + - rx + - tx + + clocks: + minItems: 3 + items: + - description: clock for TX + - description: clock for RX + - description: AHB clock driving the interface + - description: + Parent clock for mclk_tx (only required when using mclk-calibrate) + - description: + Parent clock for mclk_rx (only required when using mclk-calibrate) + - description: + Clock for sample rates that are an integer multiple of 8000 + (only required when using mclk-calibrate) + - description: + Clock for sample rates that are an integer multiple of 11025 + (only required when using mclk-calibrate) + + clock-names: + minItems: 3 + items: + - const: mclk_tx + - const: mclk_rx + - const: hclk + - const: mclk_tx_src + - const: mclk_rx_src + - const: mclk_root0 + - const: mclk_root1 + + rockchip,frame-width: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 64 + minimum: 32 + maximum: 512 + description: + Width of a frame, usually slot width multiplied by number of slots. + Must be even. + + resets: + minItems: 1 + maxItems: 2 + description: resets for the tx and rx directions + + reset-names: + minItems: 1 + maxItems: 2 + items: + enum: + - tx-m + - rx-m + + rockchip,cru: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the cru. + Required if neither trcm-sync-tx-only nor trcm-sync-rx-only are specified. + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node for the GRF register. + + rockchip,mclk-calibrate: + description: + Switch between two root clocks depending on the audio sample rate. + For integer multiples of 8000 (e.g. 48000 Hz), mclk_root0 is used. + For integer multiples of 11025 (e.g. 44100 Hz), mclk_root1 is used. + type: boolean + + rockchip,trcm-sync-tx-only: + type: boolean + description: Use TX BCLK/LRCK for both TX and RX. + + rockchip,trcm-sync-rx-only: + type: boolean + description: Use RX BCLK/LRCK for both TX and RX. + + "#sound-dai-cells": + const: 0 + + rockchip,i2s-rx-route: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Defines the mapping of I2S RX sdis to I2S data bus lines. + By default, they are mapped one-to-one. + rockchip,i2s-rx-route = <3> would mean sdi3 is receiving from data0. + maxItems: 4 + items: + - enum: [0, 1, 2, 3] + + rockchip,i2s-tx-route: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Defines the mapping of I2S TX sdos to I2S data bus lines. + By default, they are mapped one-to-one. + rockchip,i2s-tx-route = <3> would mean sdo3 is sending to data0. + maxItems: 4 + items: + - enum: [0, 1, 2, 3] + + rockchip,tdm-fsync-half-frame: + description: Whether to use half frame fsync. + type: boolean + + rockchip,io-multiplex: + description: + Specify that the GPIO lines on the I2S bus are multiplexed such that + the direction (input/output) needs to be dynamically adjusted. + type: boolean + + +required: + - compatible + - reg + - interrupts + - dmas + - dma-names + - clocks + - clock-names + - resets + - reset-names + - rockchip,grf + - "#sound-dai-cells" + +allOf: + - if: + properties: + rockchip,trcm-sync-tx-only: false + rockchip,trcm-sync-rx-only: false + then: + required: + - rockchip,cru + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3568-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/pinctrl/rockchip.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + i2s@fe410000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe410000 0x0 0x1000>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, + <&cru HCLK_I2S1_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac1 3>, <&dmac1 2>; + dma-names = "rx", "tx"; + resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,trcm-sync-tx-only; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = + <&i2s1m0_sclktx + &i2s1m0_sclkrx + &i2s1m0_lrcktx + &i2s1m0_lrckrx + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2 + &i2s1m0_sdo3>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 106d448e660d..e2cc0357e2b7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16119,6 +16119,7 @@ ROCKCHIP I2S TDM DRIVER M: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> L: linux-rockchip@lists.infradead.org S: Maintained +F: Documentation/devicetree/bindings/sound/rockchip,i2s-tdm.yaml F: sound/soc/rockchip/rockchip_i2s_tdm.* ROCKCHIP ISP V1 DRIVER
This adds the YAML bindings for the Rockchip I2S/TDM audio driver. Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> --- .../bindings/sound/rockchip,i2s-tdm.yaml | 218 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 219 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/rockchip,i2s-tdm.yaml