diff mbox series

[v2] accel/tcg/user-exec: Fix read-modify-write of code on s390 hosts

Message ID 20210803221606.150103-1-iii@linux.ibm.com (mailing list archive)
State New, archived
Headers show
Series [v2] accel/tcg/user-exec: Fix read-modify-write of code on s390 hosts | expand

Commit Message

Ilya Leoshkevich Aug. 3, 2021, 10:16 p.m. UTC
x86_64 dotnet/runtime uses cmpxchg for code patching. When running it
under s390x qemu-linux user, cpu_signal_handler() does not recognize
this as a write and does not restore PAGE_WRITE cleared by
tb_page_add(), incorrectly forwarding the signal to the guest code.

Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
---

v1: https://lists.nongnu.org/archive/html/qemu-devel/2021-08/msg00464.html
v1 -> v2: Fix comment style, fix CSST detection (Richard).

 accel/tcg/user-exec.c | 48 ++++++++++++++++++++++++++++++++++++-------
 1 file changed, 41 insertions(+), 7 deletions(-)

Comments

Richard Henderson Aug. 3, 2021, 11:54 p.m. UTC | #1
On 8/3/21 12:16 PM, Ilya Leoshkevich wrote:
> x86_64 dotnet/runtime uses cmpxchg for code patching. When running it
> under s390x qemu-linux user, cpu_signal_handler() does not recognize
> this as a write and does not restore PAGE_WRITE cleared by
> tb_page_add(), incorrectly forwarding the signal to the guest code.
> 
> Signed-off-by: Ilya Leoshkevich<iii@linux.ibm.com>
> ---
> 
> v1:https://lists.nongnu.org/archive/html/qemu-devel/2021-08/msg00464.html
> v1 -> v2: Fix comment style, fix CSST detection (Richard).
> 
>   accel/tcg/user-exec.c | 48 ++++++++++++++++++++++++++++++++++++-------
>   1 file changed, 41 insertions(+), 7 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
Ilya Leoshkevich Sept. 8, 2021, 12:16 p.m. UTC | #2
On Wed, 2021-08-04 at 00:16 +0200, Ilya Leoshkevich wrote:
> x86_64 dotnet/runtime uses cmpxchg for code patching. When running it
> under s390x qemu-linux user, cpu_signal_handler() does not recognize
> this as a write and does not restore PAGE_WRITE cleared by
> tb_page_add(), incorrectly forwarding the signal to the guest code.
> 
> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
> ---
> 
> v1:
> https://lists.nongnu.org/archive/html/qemu-devel/2021-08/msg00464.html
> v1 -> v2: Fix comment style, fix CSST detection (Richard).
> 
>  accel/tcg/user-exec.c | 48 ++++++++++++++++++++++++++++++++++++-----
> --
>  1 file changed, 41 insertions(+), 7 deletions(-)
> 
> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> index 90d1a2d327..8fed542622 100644
> --- a/accel/tcg/user-exec.c
> +++ b/accel/tcg/user-exec.c
> @@ -680,18 +680,26 @@ int cpu_signal_handler(int host_signum, void
> *pinfo,
>  
>      pc = uc->uc_mcontext.psw.addr;
>  
> -    /* ??? On linux, the non-rt signal handler has 4 (!) arguments
> instead
> -       of the normal 2 arguments.  The 3rd argument contains the
> "int_code"
> -       from the hardware which does in fact contain the is_write
> value.
> -       The rt signal handler, as far as I can tell, does not give
> this value
> -       at all.  Not that we could get to it from here even if it
> were.  */
> -    /* ??? This is not even close to complete, since it ignores all
> -       of the read-modify-write instructions.  */
> +    /*
> +     * ??? On linux, the non-rt signal handler has 4 (!) arguments
> instead
> +     * of the normal 2 arguments.  The 4th argument contains the
> "Translation-
> +     * Exception Identification for DAT Exceptions" from the
> hardware (aka
> +     * "int_parm_long"), which does in fact contain the is_write
> value.
> +     * The rt signal handler, as far as I can tell, does not give
> this value
> +     * at all.  Not that we could get to it from here even if it
> were.
> +     * So fall back to parsing instructions.  Treat read-modify-
> write ones as
> +     * writes, which is not fully correct, but for tracking self-
> modifying code
> +     * this is better than treating them as reads.  Checking si_addr
> page flags
> +     * might be a viable improvement, albeit a racy one.
> +     */
> +    /* ??? This is not even close to complete.  */
>      pinsn = (uint16_t *)pc;
>      switch (pinsn[0] >> 8) {
>      case 0x50: /* ST */
>      case 0x42: /* STC */
>      case 0x40: /* STH */
> +    case 0xba: /* CS */
> +    case 0xbb: /* CDS */
>          is_write = 1;
>          break;
>      case 0xc4: /* RIL format insns */
> @@ -702,6 +710,12 @@ int cpu_signal_handler(int host_signum, void
> *pinfo,
>              is_write = 1;
>          }
>          break;
> +    case 0xc8: /* SSF format insns */
> +        switch (pinsn[0] & 0xf) {
> +        case 0x2: /* CSST */
> +            is_write = 1;
> +        }
> +        break;
>      case 0xe3: /* RXY format insns */
>          switch (pinsn[2] & 0xff) {
>          case 0x50: /* STY */
> @@ -715,7 +729,27 @@ int cpu_signal_handler(int host_signum, void
> *pinfo,
>              is_write = 1;
>          }
>          break;
> +    case 0xeb: /* RSY format insns */
> +        switch (pinsn[2] & 0xff) {
> +        case 0x14: /* CSY */
> +        case 0x30: /* CSG */
> +        case 0x31: /* CDSY */
> +        case 0x3e: /* CDSG */
> +        case 0xe4: /* LANG */
> +        case 0xe6: /* LAOG */
> +        case 0xe7: /* LAXG */
> +        case 0xe8: /* LAAG */
> +        case 0xea: /* LAALG */
> +        case 0xf4: /* LAN */
> +        case 0xf6: /* LAO */
> +        case 0xf7: /* LAX */
> +        case 0xfa: /* LAAL */
> +        case 0xf8: /* LAA */
> +            is_write = 1;
> +        }
> +        break;
>      }
> +
>      return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
>  }
>  

Hello,

Richard has reviewed this patch a while ago - is there anything else
that needs to be done before it can be picked up?

Best regards,
Ilya
Richard Henderson Sept. 12, 2021, 10:17 p.m. UTC | #3
On 8/3/21 3:16 PM, Ilya Leoshkevich wrote:
> x86_64 dotnet/runtime uses cmpxchg for code patching. When running it
> under s390x qemu-linux user, cpu_signal_handler() does not recognize
> this as a write and does not restore PAGE_WRITE cleared by
> tb_page_add(), incorrectly forwarding the signal to the guest code.
> 
> Signed-off-by: Ilya Leoshkevich<iii@linux.ibm.com>
> ---
> 
> v1:https://lists.nongnu.org/archive/html/qemu-devel/2021-08/msg00464.html
> v1 -> v2: Fix comment style, fix CSST detection (Richard).
> 
>   accel/tcg/user-exec.c | 48 ++++++++++++++++++++++++++++++++++++-------
>   1 file changed, 41 insertions(+), 7 deletions(-)

Queued, thanks.

r~
diff mbox series

Patch

diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 90d1a2d327..8fed542622 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -680,18 +680,26 @@  int cpu_signal_handler(int host_signum, void *pinfo,
 
     pc = uc->uc_mcontext.psw.addr;
 
-    /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
-       of the normal 2 arguments.  The 3rd argument contains the "int_code"
-       from the hardware which does in fact contain the is_write value.
-       The rt signal handler, as far as I can tell, does not give this value
-       at all.  Not that we could get to it from here even if it were.  */
-    /* ??? This is not even close to complete, since it ignores all
-       of the read-modify-write instructions.  */
+    /*
+     * ??? On linux, the non-rt signal handler has 4 (!) arguments instead
+     * of the normal 2 arguments.  The 4th argument contains the "Translation-
+     * Exception Identification for DAT Exceptions" from the hardware (aka
+     * "int_parm_long"), which does in fact contain the is_write value.
+     * The rt signal handler, as far as I can tell, does not give this value
+     * at all.  Not that we could get to it from here even if it were.
+     * So fall back to parsing instructions.  Treat read-modify-write ones as
+     * writes, which is not fully correct, but for tracking self-modifying code
+     * this is better than treating them as reads.  Checking si_addr page flags
+     * might be a viable improvement, albeit a racy one.
+     */
+    /* ??? This is not even close to complete.  */
     pinsn = (uint16_t *)pc;
     switch (pinsn[0] >> 8) {
     case 0x50: /* ST */
     case 0x42: /* STC */
     case 0x40: /* STH */
+    case 0xba: /* CS */
+    case 0xbb: /* CDS */
         is_write = 1;
         break;
     case 0xc4: /* RIL format insns */
@@ -702,6 +710,12 @@  int cpu_signal_handler(int host_signum, void *pinfo,
             is_write = 1;
         }
         break;
+    case 0xc8: /* SSF format insns */
+        switch (pinsn[0] & 0xf) {
+        case 0x2: /* CSST */
+            is_write = 1;
+        }
+        break;
     case 0xe3: /* RXY format insns */
         switch (pinsn[2] & 0xff) {
         case 0x50: /* STY */
@@ -715,7 +729,27 @@  int cpu_signal_handler(int host_signum, void *pinfo,
             is_write = 1;
         }
         break;
+    case 0xeb: /* RSY format insns */
+        switch (pinsn[2] & 0xff) {
+        case 0x14: /* CSY */
+        case 0x30: /* CSG */
+        case 0x31: /* CDSY */
+        case 0x3e: /* CDSG */
+        case 0xe4: /* LANG */
+        case 0xe6: /* LAOG */
+        case 0xe7: /* LAXG */
+        case 0xe8: /* LAAG */
+        case 0xea: /* LAALG */
+        case 0xf4: /* LAN */
+        case 0xf6: /* LAO */
+        case 0xf7: /* LAX */
+        case 0xfa: /* LAAL */
+        case 0xf8: /* LAA */
+            is_write = 1;
+        }
+        break;
     }
+
     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 }