| Message ID | 20210920064133.14115-1-kishon@ti.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | PCI/gic-v3-its: Add support for same ITS device ID for multiple PCIe devices | expand |
On Mon, 20 Sep 2021 07:41:30 +0100, Kishon Vijay Abraham I <kishon@ti.com> wrote: > > AM64 has an issue in that it doesn't trigger interrupt if the address > in the *pre_its_window* is not aligned to 8-bytes (this is due to an > invalid bridge configuration in HW). > > This means there will not be interrupts for devices with PCIe > requestor ID 0x1, 0x3, 0x5..., as the address in the pre-ITS window > would be 4 (1 << 2), 12 (3 << 2), 20 (5 << 2) respectively which are > not aligned to 8-bytes. > > The DT binding has specified "msi-map-mask" using which multiple PCIe > devices could be made to use the same ITS device ID. > > Add support in irq-gic-v3-its-pci-msi.c for such cases where multiple > PCIe devices are using the same ITS device ID. > > Kishon Vijay Abraham I (3): > PCI: Add support in pci_walk_bus() to invoke callback matching RID > PCI: Export find_pci_root_bus() > irqchip/gic-v3-its: Include "msi-map-mask" for calculating nvecs > > drivers/irqchip/irq-gic-v3-its-pci-msi.c | 21 ++++++++++++++++++++- > drivers/pci/bus.c | 13 +++++++++---- > drivers/pci/host-bridge.c | 3 ++- > include/linux/pci.h | 8 ++++++-- > 4 files changed, 37 insertions(+), 8 deletions(-) What I don't see in this series is how you address the other part of the problem, which is your reuse of the Socionext hack. Please post a complete series addressing all the issues for this HW. Thanks, M.
Hi Marc, On 20/09/21 2:44 pm, Marc Zyngier wrote: > On Mon, 20 Sep 2021 07:41:30 +0100, > Kishon Vijay Abraham I <kishon@ti.com> wrote: >> >> AM64 has an issue in that it doesn't trigger interrupt if the address >> in the *pre_its_window* is not aligned to 8-bytes (this is due to an >> invalid bridge configuration in HW). >> >> This means there will not be interrupts for devices with PCIe >> requestor ID 0x1, 0x3, 0x5..., as the address in the pre-ITS window >> would be 4 (1 << 2), 12 (3 << 2), 20 (5 << 2) respectively which are >> not aligned to 8-bytes. >> >> The DT binding has specified "msi-map-mask" using which multiple PCIe >> devices could be made to use the same ITS device ID. >> >> Add support in irq-gic-v3-its-pci-msi.c for such cases where multiple >> PCIe devices are using the same ITS device ID. >> >> Kishon Vijay Abraham I (3): >> PCI: Add support in pci_walk_bus() to invoke callback matching RID >> PCI: Export find_pci_root_bus() >> irqchip/gic-v3-its: Include "msi-map-mask" for calculating nvecs >> >> drivers/irqchip/irq-gic-v3-its-pci-msi.c | 21 ++++++++++++++++++++- >> drivers/pci/bus.c | 13 +++++++++---- >> drivers/pci/host-bridge.c | 3 ++- >> include/linux/pci.h | 8 ++++++-- >> 4 files changed, 37 insertions(+), 8 deletions(-) > > What I don't see in this series is how you address the other part of > the problem, which is your reuse of the Socionext hack. Please post a > complete series addressing all the issues for this HW. No additional patches are pending. Socionext configuration is used as is https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/ti/k3-am64-main.dtsi#n72 FWIW the issue that I address in this series is not observed with standalone USB cards or NVMe cards. The issue was observed when I tried with a multi-function PCIe card. Thank You, Kishon
On Mon, 20 Sep 2021 12:22:48 +0100, Kishon Vijay Abraham I <kishon@ti.com> wrote: > > Hi Marc, > > On 20/09/21 2:44 pm, Marc Zyngier wrote: > > On Mon, 20 Sep 2021 07:41:30 +0100, > > Kishon Vijay Abraham I <kishon@ti.com> wrote: > >> > >> AM64 has an issue in that it doesn't trigger interrupt if the address > >> in the *pre_its_window* is not aligned to 8-bytes (this is due to an > >> invalid bridge configuration in HW). > >> > >> This means there will not be interrupts for devices with PCIe > >> requestor ID 0x1, 0x3, 0x5..., as the address in the pre-ITS window > >> would be 4 (1 << 2), 12 (3 << 2), 20 (5 << 2) respectively which are > >> not aligned to 8-bytes. > >> > >> The DT binding has specified "msi-map-mask" using which multiple PCIe > >> devices could be made to use the same ITS device ID. > >> > >> Add support in irq-gic-v3-its-pci-msi.c for such cases where multiple > >> PCIe devices are using the same ITS device ID. > >> > >> Kishon Vijay Abraham I (3): > >> PCI: Add support in pci_walk_bus() to invoke callback matching RID > >> PCI: Export find_pci_root_bus() > >> irqchip/gic-v3-its: Include "msi-map-mask" for calculating nvecs > >> > >> drivers/irqchip/irq-gic-v3-its-pci-msi.c | 21 ++++++++++++++++++++- > >> drivers/pci/bus.c | 13 +++++++++---- > >> drivers/pci/host-bridge.c | 3 ++- > >> include/linux/pci.h | 8 ++++++-- > >> 4 files changed, 37 insertions(+), 8 deletions(-) > > > > What I don't see in this series is how you address the other part of > > the problem, which is your reuse of the Socionext hack. Please post a > > complete series addressing all the issues for this HW. > > No additional patches are pending. Socionext configuration is used as is > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/ti/k3-am64-main.dtsi#n72 Hmmm. You are pretty lucky that the Socionext machine is also using a GIC-500, and that your pre-ITS widget falls into the low 4GB... > FWIW the issue that I address in this series is not observed with > standalone USB cards or NVMe cards. The issue was observed when I > tried with a multi-function PCIe card. That's indeed what I understood of the bug. M.