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[2/5] x86/mce/inject: Set the valid bit in MCA_STATUS before error injection

Message ID 20210915232739.6367-3-Smita.KoralahalliChannabasappa@amd.com (mailing list archive)
State New, archived
Headers show
Series x86/mce: Handle error simulation failures in mce-inject module | expand

Commit Message

Smita Koralahalli Sept. 15, 2021, 11:27 p.m. UTC 
MCA handlers check the valid bit in each status register (MCA_STATUS[Val])
and examine the remainder of the status register only if the valid bit is
set.

Set the valid bit in the corresponding MCA_STATUS register if the user
forgets to set it while doing error simulation.

Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
---
 arch/x86/kernel/cpu/mce/inject.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Borislav Petkov Sept. 24, 2021, 8:26 a.m. UTC | #1 
On Wed, Sep 15, 2021 at 06:27:36PM -0500, Smita Koralahalli wrote:
> MCA handlers check the valid bit in each status register (MCA_STATUS[Val])
> and examine the remainder of the status register only if the valid bit is
> set.
> 
> Set the valid bit in the corresponding MCA_STATUS register if the user
> forgets to set it while doing error simulation.

Why, maybe the user wants to inject with Val not set. You could warn
here instead and state that handlers will likely ignore signatures with
Val=0.
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Patch

diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c
index 51ac575c4605..8de709b049fc 100644
--- a/arch/x86/kernel/cpu/mce/inject.c
+++ b/arch/x86/kernel/cpu/mce/inject.c
@@ -490,6 +490,8 @@  static void do_inject(void)
 
 	i_mce.tsc = rdtsc_ordered();
 
+	i_mce.status |= MCI_STATUS_VAL;
+
 	if (i_mce.misc)
 		i_mce.status |= MCI_STATUS_MISCV;