| Message ID | 20210915232739.6367-4-Smita.KoralahalliChannabasappa@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | x86/mce: Handle error simulation failures in mce-inject module | expand |
On Wed, Sep 15, 2021 at 06:27:37PM -0500, Smita Koralahalli wrote: > Replace MCx_{STATUS, ADDR, MISC} macros with msr_ops. > > Also, restructure the code to avoid multiple initializations for MCA > registers. SMCA machines define a different set of MSRs for MCA registers > and msr_ops initializes appropriate MSRs for SMCA and legacy processors. > > Initialize MCA_MISC and MCA_SYND registers at the end after initializing > MCx_{STATUS, DESTAT} which is further explained in the next patch. > > Make msr_ops exportable in order to be accessible from mce-inject module. > > Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> > --- > arch/x86/kernel/cpu/mce/core.c | 1 + > arch/x86/kernel/cpu/mce/inject.c | 27 +++++++++++++-------------- > 2 files changed, 14 insertions(+), 14 deletions(-) https://git.kernel.org/tip/8121b8f947be0033f567619be204639a50cad298
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 193204aee880..9af910acb930 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -222,6 +222,7 @@ struct mca_msr_regs msr_ops = { .addr = addr_reg, .misc = misc_reg }; +EXPORT_SYMBOL_GPL(msr_ops); static void __print_mce(struct mce *m) { diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c index 8de709b049fc..8af4c9845f96 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -464,22 +464,21 @@ static void prepare_msrs(void *info) wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); - if (boot_cpu_has(X86_FEATURE_SMCA)) { - if (m.inject_flags == DFR_INT_INJ) { - wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); - wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); - } else { - wrmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); - wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); - } + if (boot_cpu_has(X86_FEATURE_SMCA) && + m.inject_flags == DFR_INT_INJ) { + wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); + wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); + goto out; + } + + wrmsrl(msr_ops.status(b), m.status); + wrmsrl(msr_ops.addr(b), m.addr); - wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); +out: + wrmsrl(msr_ops.misc(b), m.misc); + + if (boot_cpu_has(X86_FEATURE_SMCA)) wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); - } else { - wrmsrl(MSR_IA32_MCx_STATUS(b), m.status); - wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr); - wrmsrl(MSR_IA32_MCx_MISC(b), m.misc); - } } static void do_inject(void)
Replace MCx_{STATUS, ADDR, MISC} macros with msr_ops. Also, restructure the code to avoid multiple initializations for MCA registers. SMCA machines define a different set of MSRs for MCA registers and msr_ops initializes appropriate MSRs for SMCA and legacy processors. Initialize MCA_MISC and MCA_SYND registers at the end after initializing MCx_{STATUS, DESTAT} which is further explained in the next patch. Make msr_ops exportable in order to be accessible from mce-inject module. Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> --- arch/x86/kernel/cpu/mce/core.c | 1 + arch/x86/kernel/cpu/mce/inject.c | 27 +++++++++++++-------------- 2 files changed, 14 insertions(+), 14 deletions(-)