| Message ID | 20210924162321.1.Ic2904d37f30013a7f3d8476203ad3733c186827e@changeid (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] drm/rockchip: dsi: hold pm-runtime across bind/unbind | expand |
Hi, On Sat, Sep 25, 2021 at 7:24 AM Brian Norris <briannorris@chromium.org> wrote: > > In commit 59eb7193bef2, we moved most HW configuration to bind(), but we > didn't move the runtime PM management. Therefore, depending on initial > boot state, runtime-PM workqueue delays, and other timing factors, we > may disable our power domain in between the hardware configuration > (bind()) and when we enable the display. This can cause us to lose > hardware state and fail to configure our display. For example: > > dw-mipi-dsi-rockchip ff968000.mipi: failed to write command FIFO > panel-innolux-p079zca ff960000.mipi.0: failed to write command 0 > > or: > > dw-mipi-dsi-rockchip ff968000.mipi: failed to write command FIFO > panel-kingdisplay-kd097d04 ff960000.mipi.0: failed write init cmds: -110 > > We should match the runtime PM to the lifetime of the bind()/unbind() > cycle. I'm not too familiar with MIPI DSI, but it seems that the subsystem expects the DSI link to be always available, and in LPM if power saving is required? If so then this change matches that expectation, though we might lose some power savings compared to the previous non-conforming behavior. > Tested on Acer Chrometab 10 (RK3399 Gru-Scarlet), with panel drivers > built either as modules or built-in. > > Side notes: it seems one is more likely to see this problem when the > panel driver is built into the kernel. I've also seen this problem > bisect down to commits that simply changed Kconfig dependencies, because > it changed the order in which driver init functions were compiled into > the kernel, and therefore the ordering and timing of built-in device > probe. > > Fixes: 59eb7193bef2 ("drm/rockchip: dsi: move all lane config except LCDC mux to bind()") This hash is from some stable branch. The mainline one is: 43c2de1002d2 drm/rockchip: dsi: move all lane config except LCDC mux to bind() > Link: https://lore.kernel.org/linux-rockchip/9aedfb528600ecf871885f7293ca4207c84d16c1.camel@gmail.com/ > Reported-by: <aleksandr.o.makarov@gmail.com> > Cc: <stable@vger.kernel.org> > Signed-off-by: Brian Norris <briannorris@chromium.org> > --- > > .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 22 +++++++------------ > 1 file changed, 8 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c > index a2262bee5aa4..4340a99edb97 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c > @@ -773,10 +773,6 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) > if (mux < 0) > return; > > - pm_runtime_get_sync(dsi->dev); > - if (dsi->slave) > - pm_runtime_get_sync(dsi->slave->dev); > - > /* > * For the RK3399, the clk of grf must be enabled before writing grf > * register. And for RK3288 or other soc, this grf_clk must be NULL, > @@ -795,20 +791,10 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) > clk_disable_unprepare(dsi->grf_clk); > } > > -static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder) > -{ > - struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); > - > - if (dsi->slave) > - pm_runtime_put(dsi->slave->dev); > - pm_runtime_put(dsi->dev); > -} > - > static const struct drm_encoder_helper_funcs > dw_mipi_dsi_encoder_helper_funcs = { > .atomic_check = dw_mipi_dsi_encoder_atomic_check, > .enable = dw_mipi_dsi_encoder_enable, > - .disable = dw_mipi_dsi_encoder_disable, > }; > > static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, > @@ -938,6 +924,10 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev, > put_device(second); > } > > + pm_runtime_get_sync(dsi->dev); > + if (dsi->slave) > + pm_runtime_get_sync(dsi->slave->dev); > + > ret = clk_prepare_enable(dsi->pllref_clk); > if (ret) { > DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret); The bind function is missing an error cleanup path. We might end up with unbalanced runtime PM references. (And also possibly an enabled pllref clk.) This is a pre-existing issue though. The code changes here look correct. Regards ChenYu > @@ -989,6 +979,10 @@ static void dw_mipi_dsi_rockchip_unbind(struct device *dev, > dw_mipi_dsi_unbind(dsi->dmd); > > clk_disable_unprepare(dsi->pllref_clk); > + > + pm_runtime_put(dsi->dev); > + if (dsi->slave) > + pm_runtime_put(dsi->slave->dev); > } > > static const struct component_ops dw_mipi_dsi_rockchip_ops = { > -- > 2.33.0.685.g46640cef36-goog > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip
On Fri, Sep 24, 2021 at 04:23:45PM -0700, Brian Norris wrote: > In commit 59eb7193bef2, we moved most HW configuration to bind(), but we > didn't move the runtime PM management. Therefore, depending on initial > boot state, runtime-PM workqueue delays, and other timing factors, we > may disable our power domain in between the hardware configuration > (bind()) and when we enable the display. This can cause us to lose > hardware state and fail to configure our display. For example: > > dw-mipi-dsi-rockchip ff968000.mipi: failed to write command FIFO > panel-innolux-p079zca ff960000.mipi.0: failed to write command 0 > > or: > > dw-mipi-dsi-rockchip ff968000.mipi: failed to write command FIFO > panel-kingdisplay-kd097d04 ff960000.mipi.0: failed write init cmds: -110 > > We should match the runtime PM to the lifetime of the bind()/unbind() > cycle. > > Tested on Acer Chrometab 10 (RK3399 Gru-Scarlet), with panel drivers > built either as modules or built-in. > > Side notes: it seems one is more likely to see this problem when the > panel driver is built into the kernel. I've also seen this problem > bisect down to commits that simply changed Kconfig dependencies, because > it changed the order in which driver init functions were compiled into > the kernel, and therefore the ordering and timing of built-in device > probe. > > Fixes: 59eb7193bef2 ("drm/rockchip: dsi: move all lane config except LCDC mux to bind()") > Link: https://lore.kernel.org/linux-rockchip/9aedfb528600ecf871885f7293ca4207c84d16c1.camel@gmail.com/ > Reported-by: <aleksandr.o.makarov@gmail.com> > Cc: <stable@vger.kernel.org> > Signed-off-by: Brian Norris <briannorris@chromium.org> > --- This fixes the display enablement issue in Acer Chrometab 10 (RK3399 Gru-Scarlet) indeed. Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Thanks, Nícolas
On Mon, Sep 27, 2021 at 12:10 AM Chen-Yu Tsai <wenst@chromium.org> wrote: > On Sat, Sep 25, 2021 at 7:24 AM Brian Norris <briannorris@chromium.org> wrote: > > We should match the runtime PM to the lifetime of the bind()/unbind() > > cycle. > > I'm not too familiar with MIPI DSI, but it seems that the subsystem expects > the DSI link to be always available, and in LPM if power saving is required? > If so then this change matches that expectation, though we might lose some > power savings compared to the previous non-conforming behavior. Yeah, I was a little torn on whether we should care about any possible lost power savings here, because now we stay runtime-enabled even if the display is not enable()d. But I'm not aware of a good hook for handling this kind of a sequence, and I'm not convinced there is much savings by disabling the power domain in that case. > > Fixes: 59eb7193bef2 ("drm/rockchip: dsi: move all lane config except LCDC mux to bind()") > > This hash is from some stable branch. The mainline one is: > > 43c2de1002d2 drm/rockchip: dsi: move all lane config except LCDC mux to bind() Oops, good catch. I've been doing too much debugging/development on 5.10.y stable. Fixed in v2. > The bind function is missing an error cleanup path. We might end up with > unbalanced runtime PM references. (And also possibly an enabled pllref clk.) > This is a pre-existing issue though. The code changes here look correct. In v2, I've performed cleanup for the runtime PM state in this patch, and added an additional patch to fix the other existing issues you noted. Thanks. Brian
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index a2262bee5aa4..4340a99edb97 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -773,10 +773,6 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) if (mux < 0) return; - pm_runtime_get_sync(dsi->dev); - if (dsi->slave) - pm_runtime_get_sync(dsi->slave->dev); - /* * For the RK3399, the clk of grf must be enabled before writing grf * register. And for RK3288 or other soc, this grf_clk must be NULL, @@ -795,20 +791,10 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) clk_disable_unprepare(dsi->grf_clk); } -static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder) -{ - struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); - - if (dsi->slave) - pm_runtime_put(dsi->slave->dev); - pm_runtime_put(dsi->dev); -} - static const struct drm_encoder_helper_funcs dw_mipi_dsi_encoder_helper_funcs = { .atomic_check = dw_mipi_dsi_encoder_atomic_check, .enable = dw_mipi_dsi_encoder_enable, - .disable = dw_mipi_dsi_encoder_disable, }; static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, @@ -938,6 +924,10 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev, put_device(second); } + pm_runtime_get_sync(dsi->dev); + if (dsi->slave) + pm_runtime_get_sync(dsi->slave->dev); + ret = clk_prepare_enable(dsi->pllref_clk); if (ret) { DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret); @@ -989,6 +979,10 @@ static void dw_mipi_dsi_rockchip_unbind(struct device *dev, dw_mipi_dsi_unbind(dsi->dmd); clk_disable_unprepare(dsi->pllref_clk); + + pm_runtime_put(dsi->dev); + if (dsi->slave) + pm_runtime_put(dsi->slave->dev); } static const struct component_ops dw_mipi_dsi_rockchip_ops = {
In commit 59eb7193bef2, we moved most HW configuration to bind(), but we didn't move the runtime PM management. Therefore, depending on initial boot state, runtime-PM workqueue delays, and other timing factors, we may disable our power domain in between the hardware configuration (bind()) and when we enable the display. This can cause us to lose hardware state and fail to configure our display. For example: dw-mipi-dsi-rockchip ff968000.mipi: failed to write command FIFO panel-innolux-p079zca ff960000.mipi.0: failed to write command 0 or: dw-mipi-dsi-rockchip ff968000.mipi: failed to write command FIFO panel-kingdisplay-kd097d04 ff960000.mipi.0: failed write init cmds: -110 We should match the runtime PM to the lifetime of the bind()/unbind() cycle. Tested on Acer Chrometab 10 (RK3399 Gru-Scarlet), with panel drivers built either as modules or built-in. Side notes: it seems one is more likely to see this problem when the panel driver is built into the kernel. I've also seen this problem bisect down to commits that simply changed Kconfig dependencies, because it changed the order in which driver init functions were compiled into the kernel, and therefore the ordering and timing of built-in device probe. Fixes: 59eb7193bef2 ("drm/rockchip: dsi: move all lane config except LCDC mux to bind()") Link: https://lore.kernel.org/linux-rockchip/9aedfb528600ecf871885f7293ca4207c84d16c1.camel@gmail.com/ Reported-by: <aleksandr.o.makarov@gmail.com> Cc: <stable@vger.kernel.org> Signed-off-by: Brian Norris <briannorris@chromium.org> --- .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 22 +++++++------------ 1 file changed, 8 insertions(+), 14 deletions(-)