diff mbox series

[v6,26/30] tcg/loongarch64: Implement tcg_target_init

Message ID 20210925173032.2434906-27-git@xen0n.name (mailing list archive)
State New, archived
Headers show
Series LoongArch64 port of QEMU TCG | expand

Commit Message

WANG Xuerui Sept. 25, 2021, 5:30 p.m. UTC 
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/loongarch64/tcg-target.c.inc | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

Comments

Philippe Mathieu-Daudé Sept. 26, 2021, 7:15 a.m. UTC | #1 
On 9/25/21 19:30, WANG Xuerui wrote:
> Signed-off-by: WANG Xuerui <git@xen0n.name>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  tcg/loongarch64/tcg-target.c.inc | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)

> +static void tcg_target_init(TCGContext *s)
> +{
> +    tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
> +    tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
> +
> +    tcg_target_call_clobber_regs = ALL_GENERAL_REGS;

If you plan to add support for vector registers later, I think it is
safer to start today with:

       tcg_target_call_clobber_regs = -1ull;

> +    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0);
> +    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1);
> +    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2);
> +    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3);
> +    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4);
> +    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5);
> +    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6);
> +    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7);
> +    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8);
> +    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9);
> +
> +    s->reserved_regs = 0;
> +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO);
> +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0);
> +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);
> +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2);
> +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
> +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP);
> +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED);
> +}
> 

Conditional on using -1 to initialize:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Richard Henderson Sept. 26, 2021, 11:07 p.m. UTC | #2 
On 9/26/21 3:15 AM, Philippe Mathieu-Daudé wrote:
> On 9/25/21 19:30, WANG Xuerui wrote:
>> Signed-off-by: WANG Xuerui <git@xen0n.name>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>   tcg/loongarch64/tcg-target.c.inc | 27 +++++++++++++++++++++++++++
>>   1 file changed, 27 insertions(+)
> 
>> +static void tcg_target_init(TCGContext *s)
>> +{
>> +    tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
>> +    tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
>> +
>> +    tcg_target_call_clobber_regs = ALL_GENERAL_REGS;
> 
> If you plan to add support for vector registers later, I think it is
> safer to start today with:
> 
>         tcg_target_call_clobber_regs = -1ull;

It is not "safer", it is wrong -- there are bits set for which there are no registers.


r~
WANG Xuerui Sept. 29, 2021, 5 p.m. UTC | #3 
Hi Richard,

On 9/27/21 07:07, Richard Henderson wrote:
> On 9/26/21 3:15 AM, Philippe Mathieu-Daudé wrote:
>> On 9/25/21 19:30, WANG Xuerui wrote:
>>> Signed-off-by: WANG Xuerui <git@xen0n.name>
>>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>> ---
>>>   tcg/loongarch64/tcg-target.c.inc | 27 +++++++++++++++++++++++++++
>>>   1 file changed, 27 insertions(+)
>>
>>> +static void tcg_target_init(TCGContext *s)
>>> +{
>>> +    tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
>>> +    tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
>>> +
>>> +    tcg_target_call_clobber_regs = ALL_GENERAL_REGS;
>>
>> If you plan to add support for vector registers later, I think it is
>> safer to start today with:
>>
>>         tcg_target_call_clobber_regs = -1ull;
>
> It is not "safer", it is wrong -- there are bits set for which there 
> are no registers.
>
It seems this patch doesn't need touching after all, and the whole 
series have been reviewed by now; do I need to send a final revision 
with all tags collected? Or is this series just waiting for next queue 
chance / merge window? I'm not quite sure about the QEMU workflow so I'm 
asking here, apologizes if I'm pinging this too early (maybe I really 
should wait for another 3 or 4 days before asking this).
>
> r~
Philippe Mathieu-Daudé Sept. 29, 2021, 5:11 p.m. UTC | #4 
On 9/27/21 01:07, Richard Henderson wrote:
> On 9/26/21 3:15 AM, Philippe Mathieu-Daudé wrote:
>> On 9/25/21 19:30, WANG Xuerui wrote:
>>> Signed-off-by: WANG Xuerui <git@xen0n.name>
>>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>> ---
>>>   tcg/loongarch64/tcg-target.c.inc | 27 +++++++++++++++++++++++++++
>>>   1 file changed, 27 insertions(+)
>>
>>> +static void tcg_target_init(TCGContext *s)
>>> +{
>>> +    tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
>>> +    tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
>>> +
>>> +    tcg_target_call_clobber_regs = ALL_GENERAL_REGS;
>>
>> If you plan to add support for vector registers later, I think it is
>> safer to start today with:
>>
>>         tcg_target_call_clobber_regs = -1ull;
> 
> It is not "safer", it is wrong -- there are bits set for which there are
> no registers.

OK, got it now, thanks.
diff mbox series

Patch

diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index d0b8ac05c9..e3c73f9fe7 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1604,3 +1604,30 @@  static void tcg_target_qemu_prologue(TCGContext *s)
     tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
     tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_RA, 0);
 }
+
+static void tcg_target_init(TCGContext *s)
+{
+    tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
+    tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
+
+    tcg_target_call_clobber_regs = ALL_GENERAL_REGS;
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0);
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1);
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2);
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3);
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4);
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5);
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6);
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7);
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8);
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9);
+
+    s->reserved_regs = 0;
+    tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO);
+    tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0);
+    tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);
+    tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2);
+    tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
+    tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP);
+    tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED);
+}