| Message ID | 20210715065203.709914-8-vkoul@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/msm: Add Display Stream Compression Support | expand |
On 2021-07-14 23:51, Vinod Koul wrote: > We cannot enable mode_3d when we are using the DSC. So pass > configuration to detect DSC is enabled and not enable mode_3d > when we are using DSC > > We add a helper dpu_encoder_helper_get_dsc_mode() to detect dsc > enabled and pass this to .setup_intf_cfg() > This is not entirely correct. This is true only for the 2-2-1 topology you are using on this panel. When you are using 2-2-1, you are using 2 LMs, 2 DSCs and 1 DSI. So 3D mux shouldnt be used. If you are using something like 4-2-1 or 4-2-2, then you have 4LMs, 2 DSCs and 2/1 DSI. Here you need the 3D mux to convert the data from 4LMs to 2 DSCs. So please correct the commit text here and also add a check for the topology. > Signed-off-by: Vinod Koul <vkoul@kernel.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 11 +++++++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 ++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 5 +++-- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++ > 4 files changed, 18 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > index ecbc4be98980..d43b804528eb 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > @@ -336,6 +336,17 @@ static inline enum dpu_3d_blend_mode > dpu_encoder_helper_get_3d_blend_mode( > return BLEND_3D_NONE; > } > > +static inline bool dpu_encoder_helper_get_dsc_mode(struct > dpu_encoder_phys *phys_enc) > +{ > + struct drm_encoder *drm_enc = phys_enc->parent; > + struct msm_drm_private *priv = drm_enc->dev->dev_private; > + > + if (priv->dsc) > + return true; > + > + return false; > +} Check whether DSC is enabled and only if its 2-2-1 topology. This needs to be reworked when other topologies are supported. > + > /** > * dpu_encoder_helper_split_config - split display configuration > helper function > * This helper function may be used by physical encoders to configure > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > index b2be39b9144e..5fe87881c30c 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > @@ -69,6 +69,8 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( > intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD; > intf_cfg.stream_sel = cmd_enc->stream_sel; > intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); > + intf_cfg.dsc = dpu_encoder_helper_get_dsc_mode(phys_enc); > + > ctl->ops.setup_intf_cfg(ctl, &intf_cfg); > } > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > index aeea6add61ee..f059416311ee 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > @@ -121,7 +121,7 @@ static u32 dpu_hw_ctl_get_pending_flush(struct > dpu_hw_ctl *ctx) > return ctx->pending_flush_mask; > } > > -static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) > +static void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) > { > DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, BIT(0) | BIT(1) | BIT(2) | > BIT(3)); > > @@ -522,7 +522,8 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl > *ctx, > > intf_cfg |= (cfg->intf & 0xF) << 4; > > - if (cfg->mode_3d) { > + /* In DSC we can't set merge, so check for dsc too */ > + if (cfg->mode_3d && !cfg->dsc) { > intf_cfg |= BIT(19); > intf_cfg |= (cfg->mode_3d - 0x1) << 20; > } > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > index 806c171e5df2..347a653c1e01 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > @@ -39,6 +39,7 @@ struct dpu_hw_stage_cfg { > * @mode_3d: 3d mux configuration > * @merge_3d: 3d merge block used > * @intf_mode_sel: Interface mode, cmd / vid > + * @dsc: DSC is enabled > * @stream_sel: Stream selection for multi-stream > interfaces > */ > struct dpu_hw_intf_cfg { > @@ -46,6 +47,7 @@ struct dpu_hw_intf_cfg { > enum dpu_3d_blend_mode mode_3d; > enum dpu_merge_3d merge_3d; > enum dpu_ctl_mode_sel intf_mode_sel; > + bool dsc; > int stream_sel; > };
On 02-08-21, 17:24, abhinavk@codeaurora.org wrote: > On 2021-07-14 23:51, Vinod Koul wrote: > > We cannot enable mode_3d when we are using the DSC. So pass > > configuration to detect DSC is enabled and not enable mode_3d > > when we are using DSC > > > > We add a helper dpu_encoder_helper_get_dsc_mode() to detect dsc > > enabled and pass this to .setup_intf_cfg() > > > This is not entirely correct. This is true only for the 2-2-1 topology you > are using > on this panel. > > When you are using 2-2-1, you are using 2 LMs, 2 DSCs and 1 DSI. > So 3D mux shouldnt be used. > > If you are using something like 4-2-1 or 4-2-2, then you have 4LMs, > 2 DSCs and 2/1 DSI. > > Here you need the 3D mux to convert the data from 4LMs to 2 DSCs. > > So please correct the commit text here and also add a check for the > topology. Ack, we should mention this and modify it in future when more topology support is added.
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index ecbc4be98980..d43b804528eb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -336,6 +336,17 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( return BLEND_3D_NONE; } +static inline bool dpu_encoder_helper_get_dsc_mode(struct dpu_encoder_phys *phys_enc) +{ + struct drm_encoder *drm_enc = phys_enc->parent; + struct msm_drm_private *priv = drm_enc->dev->dev_private; + + if (priv->dsc) + return true; + + return false; +} + /** * dpu_encoder_helper_split_config - split display configuration helper function * This helper function may be used by physical encoders to configure diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index b2be39b9144e..5fe87881c30c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -69,6 +69,8 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD; intf_cfg.stream_sel = cmd_enc->stream_sel; intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); + intf_cfg.dsc = dpu_encoder_helper_get_dsc_mode(phys_enc); + ctl->ops.setup_intf_cfg(ctl, &intf_cfg); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index aeea6add61ee..f059416311ee 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -121,7 +121,7 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx) return ctx->pending_flush_mask; } -static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) +static void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) { DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, BIT(0) | BIT(1) | BIT(2) | BIT(3)); @@ -522,7 +522,8 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, intf_cfg |= (cfg->intf & 0xF) << 4; - if (cfg->mode_3d) { + /* In DSC we can't set merge, so check for dsc too */ + if (cfg->mode_3d && !cfg->dsc) { intf_cfg |= BIT(19); intf_cfg |= (cfg->mode_3d - 0x1) << 20; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index 806c171e5df2..347a653c1e01 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -39,6 +39,7 @@ struct dpu_hw_stage_cfg { * @mode_3d: 3d mux configuration * @merge_3d: 3d merge block used * @intf_mode_sel: Interface mode, cmd / vid + * @dsc: DSC is enabled * @stream_sel: Stream selection for multi-stream interfaces */ struct dpu_hw_intf_cfg { @@ -46,6 +47,7 @@ struct dpu_hw_intf_cfg { enum dpu_3d_blend_mode mode_3d; enum dpu_merge_3d merge_3d; enum dpu_ctl_mode_sel intf_mode_sel; + bool dsc; int stream_sel; };
We cannot enable mode_3d when we are using the DSC. So pass configuration to detect DSC is enabled and not enable mode_3d when we are using DSC We add a helper dpu_encoder_helper_get_dsc_mode() to detect dsc enabled and pass this to .setup_intf_cfg() Signed-off-by: Vinod Koul <vkoul@kernel.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 11 +++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 5 +++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++ 4 files changed, 18 insertions(+), 2 deletions(-)