| Message ID | 20211007230619.957016-2-chris.packham@alliedtelesis.co.nz (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm/arm64: dts: Enable more network hardware | expand |
On Fri, Oct 08, 2021 at 12:06:18PM +1300, Chris Packham wrote: > Enable the 2.5G Ethernet port by setting the status to "okay" and the > phy-mode to "2500base-x" on the cn9130-crb boards. Tested on a > CN9130-CRB-A. > > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > --- > > The Marvell SDK adds 2500base-t and uses it in the equivalent dtsi but > looking at the documentation for both the SoC and the PHY I think > 2500base-x is correct for the system interface (the line side is > 2500base-t). 2500base-t does not make any sense. It does not even exist in mainline. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew
Hello Chris, > Enable the 2.5G Ethernet port by setting the status to "okay" and the > phy-mode to "2500base-x" on the cn9130-crb boards. Tested on a > CN9130-CRB-A. > > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> As I am not sure that next week the pull request will be accepted when you will send the v2 for the second patch, I already applied the one on mvebu/dt64 Thanks, Gregory > --- > > The Marvell SDK adds 2500base-t and uses it in the equivalent dtsi but > looking at the documentation for both the SoC and the PHY I think > 2500base-x is correct for the system interface (the line side is > 2500base-t). > > arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi > index 505ae69289f6..e7918f325646 100644 > --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi > +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi > @@ -214,8 +214,8 @@ &cp0_eth1 { > }; > > &cp0_eth2 { > - /* This port uses "2500base-t" phy-mode */ > - status = "disabled"; > + status = "okay"; > + phy-mode = "2500base-x"; > phy = <&nbaset_phy0>; > phys = <&cp0_comphy5 2>; > }; > -- > 2.33.0 >
On 14/10/21 3:52 am, Gregory CLEMENT wrote: > Hello Chris, > >> Enable the 2.5G Ethernet port by setting the status to "okay" and the >> phy-mode to "2500base-x" on the cn9130-crb boards. Tested on a >> CN9130-CRB-A. >> >> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > As I am not sure that next week the pull request will be accepted when > you will send the v2 for the second patch, I already applied the one on > mvebu/dt64 OK thanks. This patch is independent of the switch/sfp so this should be fine. > Thanks, > > Gregory > > >> --- >> >> The Marvell SDK adds 2500base-t and uses it in the equivalent dtsi but >> looking at the documentation for both the SoC and the PHY I think >> 2500base-x is correct for the system interface (the line side is >> 2500base-t). >> >> arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi >> index 505ae69289f6..e7918f325646 100644 >> --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi >> +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi >> @@ -214,8 +214,8 @@ &cp0_eth1 { >> }; >> >> &cp0_eth2 { >> - /* This port uses "2500base-t" phy-mode */ >> - status = "disabled"; >> + status = "okay"; >> + phy-mode = "2500base-x"; >> phy = <&nbaset_phy0>; >> phys = <&cp0_comphy5 2>; >> }; >> -- >> 2.33.0 >>
Hi Gregory, On 14/10/21 3:52 am, Gregory CLEMENT wrote: > Hello Chris, > >> Enable the 2.5G Ethernet port by setting the status to "okay" and the >> phy-mode to "2500base-x" on the cn9130-crb boards. Tested on a >> CN9130-CRB-A. >> >> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > As I am not sure that next week the pull request will be accepted when > you will send the v2 for the second patch, I already applied the one on > mvebu/dt64 I pulled git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git today and can't see this patch. Am I looking in the right place? > Thanks, > > Gregory > > >> --- >> >> The Marvell SDK adds 2500base-t and uses it in the equivalent dtsi but >> looking at the documentation for both the SoC and the PHY I think >> 2500base-x is correct for the system interface (the line side is >> 2500base-t). >> >> arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi >> index 505ae69289f6..e7918f325646 100644 >> --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi >> +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi >> @@ -214,8 +214,8 @@ &cp0_eth1 { >> }; >> >> &cp0_eth2 { >> - /* This port uses "2500base-t" phy-mode */ >> - status = "disabled"; >> + status = "okay"; >> + phy-mode = "2500base-x"; >> phy = <&nbaset_phy0>; >> phys = <&cp0_comphy5 2>; >> }; >> -- >> 2.33.0 >>
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi index 505ae69289f6..e7918f325646 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -214,8 +214,8 @@ &cp0_eth1 { }; &cp0_eth2 { - /* This port uses "2500base-t" phy-mode */ - status = "disabled"; + status = "okay"; + phy-mode = "2500base-x"; phy = <&nbaset_phy0>; phys = <&cp0_comphy5 2>; };
Enable the 2.5G Ethernet port by setting the status to "okay" and the phy-mode to "2500base-x" on the cn9130-crb boards. Tested on a CN9130-CRB-A. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> --- The Marvell SDK adds 2500base-t and uses it in the equivalent dtsi but looking at the documentation for both the SoC and the PHY I think 2500base-x is correct for the system interface (the line side is 2500base-t). arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)