| Message ID | 20211006095355.59078-1-amelie.delaunay@foss.st.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/1] ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151 | expand |
On 10/6/21 11:53 AM, Amelie Delaunay wrote: > Referring to the note under USBH reset and clocks chapter of RM0436, > "In order to access USBH_OHCI registers it is necessary to activate the USB > clocks by enabling the PLL controlled by USBPHYC" (ck_usbo_48m). > > The point is, when USBPHYC PLL is not enabled, OHCI register access > freezes the resume from STANDBY. It is the case when dual USBH is enabled, > instead of OTG + single USBH. > When OTG is probed, as ck_usbo_48m is USBO clock parent, then USBPHYC PLL > is enabled and OHCI register access is OK. > > This patch adds ck_usbo_48m (provided by USBPHYC PLL) as clock of USBH > OHCI, thus USBPHYC PLL will be enabled and OHCI register access will be OK. > > Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> > --- > arch/arm/boot/dts/stm32mp151.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi > index bd289bf5d269..fe194c787e6c 100644 > --- a/arch/arm/boot/dts/stm32mp151.dtsi > +++ b/arch/arm/boot/dts/stm32mp151.dtsi > @@ -1452,7 +1452,7 @@ stmmac_axi_config_0: stmmac-axi-config { > usbh_ohci: usb@5800c000 { > compatible = "generic-ohci"; > reg = <0x5800c000 0x1000>; > - clocks = <&rcc USBH>; > + clocks = <&rcc USBH>, <&usbphyc>; > resets = <&rcc USBH_R>; > interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; > status = "disabled"; > Applied on stm32-next regards Alex
diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index bd289bf5d269..fe194c787e6c 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1452,7 +1452,7 @@ stmmac_axi_config_0: stmmac-axi-config { usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; - clocks = <&rcc USBH>; + clocks = <&rcc USBH>, <&usbphyc>; resets = <&rcc USBH_R>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; status = "disabled";
Referring to the note under USBH reset and clocks chapter of RM0436, "In order to access USBH_OHCI registers it is necessary to activate the USB clocks by enabling the PLL controlled by USBPHYC" (ck_usbo_48m). The point is, when USBPHYC PLL is not enabled, OHCI register access freezes the resume from STANDBY. It is the case when dual USBH is enabled, instead of OTG + single USBH. When OTG is probed, as ck_usbo_48m is USBO clock parent, then USBPHYC PLL is enabled and OHCI register access is OK. This patch adds ck_usbo_48m (provided by USBPHYC PLL) as clock of USBH OHCI, thus USBPHYC PLL will be enabled and OHCI register access will be OK. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> --- arch/arm/boot/dts/stm32mp151.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)