| Message ID | 20211018065207.30587-4-vandita.kulkarni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable MIPI DSI video mode on ADLP | expand |
On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote: > MIPI DSI transcoder cannot be in video mode to support any of the > display C states. Imre, could you review this one please? The added confusion is that POWER_DOMAIN_TRANSCODER_DSI_A and POWER_DOMAIN_TRANSCODER_DSI_C are never used anywhere and POWER_DOMAIN_TRANSCODER() does not take DSI transcoders into account. > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display_power.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index 709569211c85..8406db5e573e 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -3105,7 +3105,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, > BIT_ULL(POWER_DOMAIN_MODESET) | \ > BIT_ULL(POWER_DOMAIN_AUX_A) | \ > BIT_ULL(POWER_DOMAIN_AUX_B) | \ > - BIT_ULL(POWER_DOMAIN_INIT)) > + BIT_ULL(POWER_DOMAIN_INIT)) | \ > + BIT_ULL(POWER_DOMAIN_PORT_DSI) Everywhere else POWER_DOMAIN_INIT is last in the list. BR, Jani. > > #define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) > #define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_XELPD)
On Tue, Oct 19, 2021 at 01:24:51PM +0300, Jani Nikula wrote: > On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote: > > MIPI DSI transcoder cannot be in video mode to support any of the > > display C states. > > Imre, could you review this one please? > > The added confusion is that POWER_DOMAIN_TRANSCODER_DSI_A and > POWER_DOMAIN_TRANSCODER_DSI_C are never used anywhere and > POWER_DOMAIN_TRANSCODER() does not take DSI transcoders into account. <tl;dr> You mean they are not listed in the power_domain->power_well mappings. Those power domains don't use any power wells above PW#1. PW#0/1 is handled "automatically" by DMC, so we don't have to toggle the power for those manually. However they still need a runtime PM reference, since whatever HW domain you want to use, the PCI device must be in the runtime resumed state. This is ensured by the always-on power well, which every domain has a dependency on. <tl;dr> The transcoder power domains are acquired in get_crtc_power_domains(), doesn't the DSI encoder using the DSI_A/C transcoders? Yes, POWER_DOMAIN_TRANSCODER is now broken wrt. DSI due to POWER_DOMAIN_TRANSCODER_VDSC_PW2. So that would need to be moved after the TRANSCODER_DSI_C. And the POWER_DOMAIN_TRANSCODER macro could be also simplified afaics. Otherwise this patch looks ok to me, just the bspec links would be good to have here too. > > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display_power.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > > index 709569211c85..8406db5e573e 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > > @@ -3105,7 +3105,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, > > BIT_ULL(POWER_DOMAIN_MODESET) | \ > > BIT_ULL(POWER_DOMAIN_AUX_A) | \ > > BIT_ULL(POWER_DOMAIN_AUX_B) | \ > > - BIT_ULL(POWER_DOMAIN_INIT)) > > + BIT_ULL(POWER_DOMAIN_INIT)) | \ > > + BIT_ULL(POWER_DOMAIN_PORT_DSI) > > Everywhere else POWER_DOMAIN_INIT is last in the list. > > BR, > Jani. > > > > > #define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) > > #define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_XELPD) > > -- > Jani Nikula, Intel Open Source Graphics Center
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 709569211c85..8406db5e573e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -3105,7 +3105,8 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, BIT_ULL(POWER_DOMAIN_MODESET) | \ BIT_ULL(POWER_DOMAIN_AUX_A) | \ BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_INIT)) + BIT_ULL(POWER_DOMAIN_INIT)) | \ + BIT_ULL(POWER_DOMAIN_PORT_DSI) #define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) #define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_XELPD)
MIPI DSI transcoder cannot be in video mode to support any of the display C states. Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> --- drivers/gpu/drm/i915/display/intel_display_power.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)