| Message ID | 20211020093603.28653-1-heinrich.schuchardt@canonical.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/1] dt-bindings: T-HEAD CLINT | expand |
On Wed, Oct 20, 2021 at 3:06 PM Heinrich Schuchardt <heinrich.schuchardt@canonical.com> wrote: > > The CLINT in the T-HEAD 9xx CPUs is similar to the SiFive CLINT but does > not support 64bit mmio access to the MTIMER device. > > OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the > restriction and the "sifive,cling0" compatible string. An OpenSBI > patch suggested to use "reg-io-width = <4>;" as the reg-io-width property > is generally used in the devicetree schema for such a condition. > > As the design is not SiFive based it is preferable to apply a compatible > string identifying T-HEAD instead. > > Add a new yaml file describing the T-HEAD CLINT. > > Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> > --- > @Palmer, @Anup > I copied you as maintainers from sifive,clint.yaml. Please, indicate if > this should be changed. > > For the prior discussion see: > https://lore.kernel.org/all/20211015100941.17621-1-heinrich.schuchardt@canonical.com/ > https://lore.kernel.org/all/20211015120735.27972-1-heinrich.schuchardt@canonical.com/ > > A release candidate of the ACLINT specification is available at > https://github.com/riscv/riscv-aclint/releases T-HEAD supporting only 32bit accesses to MTIME and MTIMECMP registers are totally allowed. The RISC-V privileged specification does not enforce RV64 platforms to support 64bit accesses to MTIME and MTIMECMP registers. Also, the ACLINT specification only states that MTIME and MTIMECMP registers are 64-bit wide but it does not enforce platforms to support 64-bit accesses. Here are some discussions from tech-aia mailing list: https://lists.riscv.org/g/tech-aia/message/115 https://lists.riscv.org/g/tech-aia/message/119 https://lists.riscv.org/g/tech-aia/message/120 In other words, the T-HEAD CLINT (MTIMER+MSWI) is compliant with the RISC-V ACLINT specification. I think we should add implementation specific compatible strings for Allwinner D1 in the ACLINT MTIMER and ACLINT MSWI DT bindings. How about including the following two compatible strings in ACLINT DT bindings ? allwinner,sun20i-d1-aclint-mtimer allwinner,sun20i-d1-aclint-mswi Regards, Anup > --- > .../bindings/timer/thead,clint.yaml | 62 +++++++++++++++++++ > 1 file changed, 62 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/thead,clint.yaml > > diff --git a/Documentation/devicetree/bindings/timer/thead,clint.yaml b/Documentation/devicetree/bindings/timer/thead,clint.yaml > new file mode 100644 > index 000000000000..02463fb2043a > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/thead,clint.yaml > @@ -0,0 +1,62 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/timer/thead,clint.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SiFive Core Local Interruptor > + > +maintainers: > + - Palmer Dabbelt <palmer@dabbelt.com> > + - Anup Patel <anup.patel@wdc.com> > + > +description: > + T-HEAD (and other RISC-V) SOCs include an implementation of the T-HEAD > + Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor > + interrupts. It directly connects to the timer and inter-processor interrupt > + lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local > + interrupt controller is the parent interrupt controller for CLINT device. > + The clock frequency of the CLINT is specified via "timebase-frequency" DT > + property of "/cpus" DT node. The "timebase-frequency" DT property is > + described in Documentation/devicetree/bindings/riscv/cpus.yaml > + > +properties: > + compatible: > + items: > + - const: > + - allwinner,sun20i-d1-clint > + - const: > + - thead,clint0 > + > + description: > + Should be "<vendor>,<chip>-clint" and "thead,clint<version>" for > + the T-HEAD derived CLINTs. > + Supported compatible strings are - > + "allwinner,sun20i-d1-clint" for the CLINT in the Allwinner D1 SoC > + and "thead,clint0" for the T-HEAD IP block with no chip > + integration tweaks. > + > + reg: > + maxItems: 1 > + > + interrupts-extended: > + minItems: 1 > + > +additionalProperties: false > + > +required: > + - compatible > + - reg > + - interrupts-extended > + > +examples: > + - | > + timer@2000000 { > + compatible = "allwinner,sun20i-d1-clint", "thead,clint0"; > + interrupts-extended = <&cpu1intc 3 &cpu1intc 7 > + &cpu2intc 3 &cpu2intc 7 > + &cpu3intc 3 &cpu3intc 7 > + &cpu4intc 3 &cpu4intc 7>; > + reg = <0x2000000 0x10000>; > + }; > +... > -- > 2.32.0 >
On 20 Oct 2021, at 12:27, Anup Patel <anup@brainfault.org> wrote: > > On Wed, Oct 20, 2021 at 3:06 PM Heinrich Schuchardt > <heinrich.schuchardt@canonical.com> wrote: >> >> The CLINT in the T-HEAD 9xx CPUs is similar to the SiFive CLINT but does >> not support 64bit mmio access to the MTIMER device. >> >> OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the >> restriction and the "sifive,cling0" compatible string. An OpenSBI >> patch suggested to use "reg-io-width = <4>;" as the reg-io-width property >> is generally used in the devicetree schema for such a condition. >> >> As the design is not SiFive based it is preferable to apply a compatible >> string identifying T-HEAD instead. >> >> Add a new yaml file describing the T-HEAD CLINT. >> >> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> >> --- >> @Palmer, @Anup >> I copied you as maintainers from sifive,clint.yaml. Please, indicate if >> this should be changed. >> >> For the prior discussion see: >> https://lore.kernel.org/all/20211015100941.17621-1-heinrich.schuchardt@canonical.com/ >> https://lore.kernel.org/all/20211015120735.27972-1-heinrich.schuchardt@canonical.com/ >> >> A release candidate of the ACLINT specification is available at >> https://github.com/riscv/riscv-aclint/releases > > T-HEAD supporting only 32bit accesses to MTIME and MTIMECMP > registers are totally allowed. The RISC-V privileged specification does > not enforce RV64 platforms to support 64bit accesses to MTIME and > MTIMECMP registers It does. See [1]. Jess [1] https://github.com/riscv/riscv-isa-manual/commit/50694a2c0d5393690a9e0c8d309cf064f6c8c0e4
On 10/20/21 13:27, Anup Patel wrote: > On Wed, Oct 20, 2021 at 3:06 PM Heinrich Schuchardt > <heinrich.schuchardt@canonical.com> wrote: >> >> The CLINT in the T-HEAD 9xx CPUs is similar to the SiFive CLINT but does >> not support 64bit mmio access to the MTIMER device. >> >> OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the >> restriction and the "sifive,cling0" compatible string. An OpenSBI >> patch suggested to use "reg-io-width = <4>;" as the reg-io-width property >> is generally used in the devicetree schema for such a condition. >> >> As the design is not SiFive based it is preferable to apply a compatible >> string identifying T-HEAD instead. >> >> Add a new yaml file describing the T-HEAD CLINT. >> >> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> >> --- >> @Palmer, @Anup >> I copied you as maintainers from sifive,clint.yaml. Please, indicate if >> this should be changed. >> >> For the prior discussion see: >> https://lore.kernel.org/all/20211015100941.17621-1-heinrich.schuchardt@canonical.com/ >> https://lore.kernel.org/all/20211015120735.27972-1-heinrich.schuchardt@canonical.com/ >> >> A release candidate of the ACLINT specification is available at >> https://github.com/riscv/riscv-aclint/releases > > T-HEAD supporting only 32bit accesses to MTIME and MTIMECMP > registers are totally allowed. The RISC-V privileged specification does > not enforce RV64 platforms to support 64bit accesses to MTIME and > MTIMECMP registers. Also, the ACLINT specification only states > that MTIME and MTIMECMP registers are 64-bit wide but it does > not enforce platforms to support 64-bit accesses. > > Here are some discussions from tech-aia mailing list: > https://lists.riscv.org/g/tech-aia/message/115 > https://lists.riscv.org/g/tech-aia/message/119 > https://lists.riscv.org/g/tech-aia/message/120 > > In other words, the T-HEAD CLINT (MTIMER+MSWI) is compliant > with the RISC-V ACLINT specification. > > I think we should add implementation specific compatible strings > for Allwinner D1 in the ACLINT MTIMER and ACLINT MSWI > DT bindings. > > How about including the following two compatible strings in > ACLINT DT bindings ? > allwinner,sun20i-d1-aclint-mtimer > allwinner,sun20i-d1-aclint-mswi If the Allwinner CLINT is sufficiently compliant, this makes sense to me. Will there be a new round of [RFC PATCH v4 08/10] dt-bindings: timer: Add ACLINT MTIMER bindings https://lore.kernel.org/all/20211007123632.697666-9-anup.patel@wdc.com/ were you could add the Allwinner device? Or is that series already merged? Should the riscv,aclint-mtimer.yaml file mention that there are different access sizes and either state per compatibility string what that size is or provide a parameter for that purpose? Best regards Heinrich > > Regards, > Anup > >> --- >> .../bindings/timer/thead,clint.yaml | 62 +++++++++++++++++++ >> 1 file changed, 62 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/timer/thead,clint.yaml >> >> diff --git a/Documentation/devicetree/bindings/timer/thead,clint.yaml b/Documentation/devicetree/bindings/timer/thead,clint.yaml >> new file mode 100644 >> index 000000000000..02463fb2043a >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/timer/thead,clint.yaml >> @@ -0,0 +1,62 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/timer/thead,clint.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: SiFive Core Local Interruptor >> + >> +maintainers: >> + - Palmer Dabbelt <palmer@dabbelt.com> >> + - Anup Patel <anup.patel@wdc.com> >> + >> +description: >> + T-HEAD (and other RISC-V) SOCs include an implementation of the T-HEAD >> + Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor >> + interrupts. It directly connects to the timer and inter-processor interrupt >> + lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local >> + interrupt controller is the parent interrupt controller for CLINT device. >> + The clock frequency of the CLINT is specified via "timebase-frequency" DT >> + property of "/cpus" DT node. The "timebase-frequency" DT property is >> + described in Documentation/devicetree/bindings/riscv/cpus.yaml >> + >> +properties: >> + compatible: >> + items: >> + - const: >> + - allwinner,sun20i-d1-clint >> + - const: >> + - thead,clint0 >> + >> + description: >> + Should be "<vendor>,<chip>-clint" and "thead,clint<version>" for >> + the T-HEAD derived CLINTs. >> + Supported compatible strings are - >> + "allwinner,sun20i-d1-clint" for the CLINT in the Allwinner D1 SoC >> + and "thead,clint0" for the T-HEAD IP block with no chip >> + integration tweaks. >> + >> + reg: >> + maxItems: 1 >> + >> + interrupts-extended: >> + minItems: 1 >> + >> +additionalProperties: false >> + >> +required: >> + - compatible >> + - reg >> + - interrupts-extended >> + >> +examples: >> + - | >> + timer@2000000 { >> + compatible = "allwinner,sun20i-d1-clint", "thead,clint0"; >> + interrupts-extended = <&cpu1intc 3 &cpu1intc 7 >> + &cpu2intc 3 &cpu2intc 7 >> + &cpu3intc 3 &cpu3intc 7 >> + &cpu4intc 3 &cpu4intc 7>; >> + reg = <0x2000000 0x10000>; >> + }; >> +... >> -- >> 2.32.0 >>
On Wed, 20 Oct 2021 11:36:03 +0200, Heinrich Schuchardt wrote: > The CLINT in the T-HEAD 9xx CPUs is similar to the SiFive CLINT but does > not support 64bit mmio access to the MTIMER device. > > OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the > restriction and the "sifive,cling0" compatible string. An OpenSBI > patch suggested to use "reg-io-width = <4>;" as the reg-io-width property > is generally used in the devicetree schema for such a condition. > > As the design is not SiFive based it is preferable to apply a compatible > string identifying T-HEAD instead. > > Add a new yaml file describing the T-HEAD CLINT. > > Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> > --- > @Palmer, @Anup > I copied you as maintainers from sifive,clint.yaml. Please, indicate if > this should be changed. > > For the prior discussion see: > https://lore.kernel.org/all/20211015100941.17621-1-heinrich.schuchardt@canonical.com/ > https://lore.kernel.org/all/20211015120735.27972-1-heinrich.schuchardt@canonical.com/ > > A release candidate of the ACLINT specification is available at > https://github.com/riscv/riscv-aclint/releases > --- > .../bindings/timer/thead,clint.yaml | 62 +++++++++++++++++++ > 1 file changed, 62 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/thead,clint.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/timer/thead,clint.yaml: properties:compatible:items: 'oneOf' conditional failed, one must be fixed: [{'const': ['allwinner,sun20i-d1-clint']}, {'const': ['thead,clint0']}] is not of type 'object' ['allwinner,sun20i-d1-clint'] is not of type 'string' ['thead,clint0'] is not of type 'string' from schema $id: http://devicetree.org/meta-schemas/string-array.yaml# /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/timer/thead,clint.yaml: ignoring, error in schema: properties: compatible: items warning: no schema found in file: ./Documentation/devicetree/bindings/timer/thead,clint.yaml Documentation/devicetree/bindings/timer/thead,clint.example.dt.yaml:0:0: /example-0/timer@2000000: failed to match any schema with compatible: ['allwinner,sun20i-d1-clint', 'thead,clint0'] Documentation/devicetree/bindings/timer/thead,clint.example.dt.yaml:0:0: /example-0/timer@2000000: failed to match any schema with compatible: ['allwinner,sun20i-d1-clint', 'thead,clint0'] doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1543771 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On Wed, Oct 20, 2021 at 5:12 PM Heinrich Schuchardt <heinrich.schuchardt@canonical.com> wrote: > > On 10/20/21 13:27, Anup Patel wrote: > > On Wed, Oct 20, 2021 at 3:06 PM Heinrich Schuchardt > > <heinrich.schuchardt@canonical.com> wrote: > >> > >> The CLINT in the T-HEAD 9xx CPUs is similar to the SiFive CLINT but does > >> not support 64bit mmio access to the MTIMER device. > >> > >> OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the > >> restriction and the "sifive,cling0" compatible string. An OpenSBI > >> patch suggested to use "reg-io-width = <4>;" as the reg-io-width property > >> is generally used in the devicetree schema for such a condition. > >> > >> As the design is not SiFive based it is preferable to apply a compatible > >> string identifying T-HEAD instead. > >> > >> Add a new yaml file describing the T-HEAD CLINT. > >> > >> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> > >> --- > >> @Palmer, @Anup > >> I copied you as maintainers from sifive,clint.yaml. Please, indicate if > >> this should be changed. > >> > >> For the prior discussion see: > >> https://lore.kernel.org/all/20211015100941.17621-1-heinrich.schuchardt@canonical.com/ > >> https://lore.kernel.org/all/20211015120735.27972-1-heinrich.schuchardt@canonical.com/ > >> > >> A release candidate of the ACLINT specification is available at > >> https://github.com/riscv/riscv-aclint/releases > > > > T-HEAD supporting only 32bit accesses to MTIME and MTIMECMP > > registers are totally allowed. The RISC-V privileged specification does > > not enforce RV64 platforms to support 64bit accesses to MTIME and > > MTIMECMP registers. Also, the ACLINT specification only states > > that MTIME and MTIMECMP registers are 64-bit wide but it does > > not enforce platforms to support 64-bit accesses. > > > > Here are some discussions from tech-aia mailing list: > > https://lists.riscv.org/g/tech-aia/message/115 > > https://lists.riscv.org/g/tech-aia/message/119 > > https://lists.riscv.org/g/tech-aia/message/120 > > > > In other words, the T-HEAD CLINT (MTIMER+MSWI) is compliant > > with the RISC-V ACLINT specification. > > > > I think we should add implementation specific compatible strings > > for Allwinner D1 in the ACLINT MTIMER and ACLINT MSWI > > DT bindings. > > > > How about including the following two compatible strings in > > ACLINT DT bindings ? > > allwinner,sun20i-d1-aclint-mtimer > > allwinner,sun20i-d1-aclint-mswi > > If the Allwinner CLINT is sufficiently compliant, this makes sense to me. > > Will there be a new round of > [RFC PATCH v4 08/10] dt-bindings: timer: Add ACLINT MTIMER bindings > https://lore.kernel.org/all/20211007123632.697666-9-anup.patel@wdc.com/ > were you could add the Allwinner device? Or is that series already merged? The Linux ACLINT series is not merged yet so there will be another patch revision as we get more review comments. I am hoping for more reviews. > > Should the riscv,aclint-mtimer.yaml file mention that there are > different access sizes and either state per compatibility string what > that size is or provide a parameter for that purpose? Should we just say that "some of the MTIMER implementations support only 32-bit accesses so this information can be derived from implementation specific compatible strings" ? Regards, Anup > > Best regards > > Heinrich > > > > > Regards, > > Anup > > > >> --- > >> .../bindings/timer/thead,clint.yaml | 62 +++++++++++++++++++ > >> 1 file changed, 62 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/timer/thead,clint.yaml > >> > >> diff --git a/Documentation/devicetree/bindings/timer/thead,clint.yaml b/Documentation/devicetree/bindings/timer/thead,clint.yaml > >> new file mode 100644 > >> index 000000000000..02463fb2043a > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/timer/thead,clint.yaml > >> @@ -0,0 +1,62 @@ > >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > >> +%YAML 1.2 > >> +--- > >> +$id: http://devicetree.org/schemas/timer/thead,clint.yaml# > >> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >> + > >> +title: SiFive Core Local Interruptor > >> + > >> +maintainers: > >> + - Palmer Dabbelt <palmer@dabbelt.com> > >> + - Anup Patel <anup.patel@wdc.com> > >> + > >> +description: > >> + T-HEAD (and other RISC-V) SOCs include an implementation of the T-HEAD > >> + Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor > >> + interrupts. It directly connects to the timer and inter-processor interrupt > >> + lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local > >> + interrupt controller is the parent interrupt controller for CLINT device. > >> + The clock frequency of the CLINT is specified via "timebase-frequency" DT > >> + property of "/cpus" DT node. The "timebase-frequency" DT property is > >> + described in Documentation/devicetree/bindings/riscv/cpus.yaml > >> + > >> +properties: > >> + compatible: > >> + items: > >> + - const: > >> + - allwinner,sun20i-d1-clint > >> + - const: > >> + - thead,clint0 > >> + > >> + description: > >> + Should be "<vendor>,<chip>-clint" and "thead,clint<version>" for > >> + the T-HEAD derived CLINTs. > >> + Supported compatible strings are - > >> + "allwinner,sun20i-d1-clint" for the CLINT in the Allwinner D1 SoC > >> + and "thead,clint0" for the T-HEAD IP block with no chip > >> + integration tweaks. > >> + > >> + reg: > >> + maxItems: 1 > >> + > >> + interrupts-extended: > >> + minItems: 1 > >> + > >> +additionalProperties: false > >> + > >> +required: > >> + - compatible > >> + - reg > >> + - interrupts-extended > >> + > >> +examples: > >> + - | > >> + timer@2000000 { > >> + compatible = "allwinner,sun20i-d1-clint", "thead,clint0"; > >> + interrupts-extended = <&cpu1intc 3 &cpu1intc 7 > >> + &cpu2intc 3 &cpu2intc 7 > >> + &cpu3intc 3 &cpu3intc 7 > >> + &cpu4intc 3 &cpu4intc 7>; > >> + reg = <0x2000000 0x10000>; > >> + }; > >> +... > >> -- > >> 2.32.0 > >> >
On Wed, Oct 20, 2021 at 11:36:03AM +0200, Heinrich Schuchardt wrote: > The CLINT in the T-HEAD 9xx CPUs is similar to the SiFive CLINT but does > not support 64bit mmio access to the MTIMER device. > > OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the > restriction and the "sifive,cling0" compatible string. An OpenSBI > patch suggested to use "reg-io-width = <4>;" as the reg-io-width property > is generally used in the devicetree schema for such a condition. > > As the design is not SiFive based it is preferable to apply a compatible > string identifying T-HEAD instead. > > Add a new yaml file describing the T-HEAD CLINT. > > Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> > --- > @Palmer, @Anup > I copied you as maintainers from sifive,clint.yaml. Please, indicate if > this should be changed. > > For the prior discussion see: > https://lore.kernel.org/all/20211015100941.17621-1-heinrich.schuchardt@canonical.com/ > https://lore.kernel.org/all/20211015120735.27972-1-heinrich.schuchardt@canonical.com/ > > A release candidate of the ACLINT specification is available at > https://github.com/riscv/riscv-aclint/releases > --- > .../bindings/timer/thead,clint.yaml | 62 +++++++++++++++++++ > 1 file changed, 62 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/thead,clint.yaml > > diff --git a/Documentation/devicetree/bindings/timer/thead,clint.yaml b/Documentation/devicetree/bindings/timer/thead,clint.yaml > new file mode 100644 > index 000000000000..02463fb2043a > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/thead,clint.yaml > @@ -0,0 +1,62 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/timer/thead,clint.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SiFive Core Local Interruptor > + > +maintainers: > + - Palmer Dabbelt <palmer@dabbelt.com> > + - Anup Patel <anup.patel@wdc.com> > + > +description: > + T-HEAD (and other RISC-V) SOCs include an implementation of the T-HEAD > + Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor > + interrupts. It directly connects to the timer and inter-processor interrupt > + lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local > + interrupt controller is the parent interrupt controller for CLINT device. > + The clock frequency of the CLINT is specified via "timebase-frequency" DT > + property of "/cpus" DT node. The "timebase-frequency" DT property is > + described in Documentation/devicetree/bindings/riscv/cpus.yaml > + > +properties: > + compatible: > + items: > + - const: > + - allwinner,sun20i-d1-clint > + - const: > + - thead,clint0 > + > + description: > + Should be "<vendor>,<chip>-clint" and "thead,clint<version>" for > + the T-HEAD derived CLINTs. > + Supported compatible strings are - > + "allwinner,sun20i-d1-clint" for the CLINT in the Allwinner D1 SoC > + and "thead,clint0" for the T-HEAD IP block with no chip > + integration tweaks. T-HEAD uses the same versioning as SiFive? If you use version numbers in compatible strings, the numbering needs to be documented and correlate back to the h/w design. See [1]. IP release numbers for FPGA IP for example. What it should not be is the binding author making up 0, 1, 2, etc. versions. Rob [1] Documentation/devicetree/bindings/sifive/sifive-blocks-ip-versioning.txt
On 10/22/21 23:22, Rob Herring wrote: > On Wed, Oct 20, 2021 at 11:36:03AM +0200, Heinrich Schuchardt wrote: >> The CLINT in the T-HEAD 9xx CPUs is similar to the SiFive CLINT but does >> not support 64bit mmio access to the MTIMER device. >> >> OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the >> restriction and the "sifive,cling0" compatible string. An OpenSBI >> patch suggested to use "reg-io-width = <4>;" as the reg-io-width property >> is generally used in the devicetree schema for such a condition. >> >> As the design is not SiFive based it is preferable to apply a compatible >> string identifying T-HEAD instead. >> >> Add a new yaml file describing the T-HEAD CLINT. >> >> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> >> --- >> @Palmer, @Anup >> I copied you as maintainers from sifive,clint.yaml. Please, indicate if >> this should be changed. >> >> For the prior discussion see: >> https://lore.kernel.org/all/20211015100941.17621-1-heinrich.schuchardt@canonical.com/ >> https://lore.kernel.org/all/20211015120735.27972-1-heinrich.schuchardt@canonical.com/ >> >> A release candidate of the ACLINT specification is available at >> https://github.com/riscv/riscv-aclint/releases >> --- >> .../bindings/timer/thead,clint.yaml | 62 +++++++++++++++++++ >> 1 file changed, 62 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/timer/thead,clint.yaml >> >> diff --git a/Documentation/devicetree/bindings/timer/thead,clint.yaml b/Documentation/devicetree/bindings/timer/thead,clint.yaml >> new file mode 100644 >> index 000000000000..02463fb2043a >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/timer/thead,clint.yaml >> @@ -0,0 +1,62 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/timer/thead,clint.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: SiFive Core Local Interruptor >> + >> +maintainers: >> + - Palmer Dabbelt <palmer@dabbelt.com> >> + - Anup Patel <anup.patel@wdc.com> >> + >> +description: >> + T-HEAD (and other RISC-V) SOCs include an implementation of the T-HEAD >> + Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor >> + interrupts. It directly connects to the timer and inter-processor interrupt >> + lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local >> + interrupt controller is the parent interrupt controller for CLINT device. >> + The clock frequency of the CLINT is specified via "timebase-frequency" DT >> + property of "/cpus" DT node. The "timebase-frequency" DT property is >> + described in Documentation/devicetree/bindings/riscv/cpus.yaml >> + >> +properties: >> + compatible: >> + items: >> + - const: >> + - allwinner,sun20i-d1-clint >> + - const: >> + - thead,clint0 >> + >> + description: >> + Should be "<vendor>,<chip>-clint" and "thead,clint<version>" for >> + the T-HEAD derived CLINTs. >> + Supported compatible strings are - >> + "allwinner,sun20i-d1-clint" for the CLINT in the Allwinner D1 SoC >> + and "thead,clint0" for the T-HEAD IP block with no chip >> + integration tweaks. > > T-HEAD uses the same versioning as SiFive? If you use version numbers in > compatible strings, the numbering needs to be documented and correlate > back to the h/w design. See [1]. IP release numbers for FPGA IP for > example. What it should not be is the binding author making up 0, 1, 2, > etc. versions. The only publicly available information on the IP block is: https://github.com/T-head-Semi/openc906/blob/main/doc/%E7%8E%84%E9%93%81C906%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf Page 3 has a version number for the whole document. Chapter 9 does not have any version number for the CLINT. So should we simply call the block "thead,clint" without any version number? @Guo: do you have more information accessible? Best regards Heinrich > > Rob > > [1] Documentation/devicetree/bindings/sifive/sifive-blocks-ip-versioning.txt >
On Sat, Oct 23, 2021 at 8:03 AM Heinrich Schuchardt <heinrich.schuchardt@canonical.com> wrote: > > > > On 10/22/21 23:22, Rob Herring wrote: > > On Wed, Oct 20, 2021 at 11:36:03AM +0200, Heinrich Schuchardt wrote: > >> The CLINT in the T-HEAD 9xx CPUs is similar to the SiFive CLINT but does > >> not support 64bit mmio access to the MTIMER device. > >> > >> OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the > >> restriction and the "sifive,cling0" compatible string. An OpenSBI > >> patch suggested to use "reg-io-width = <4>;" as the reg-io-width property > >> is generally used in the devicetree schema for such a condition. > >> > >> As the design is not SiFive based it is preferable to apply a compatible > >> string identifying T-HEAD instead. > >> > >> Add a new yaml file describing the T-HEAD CLINT. > >> > >> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> > >> --- > >> @Palmer, @Anup > >> I copied you as maintainers from sifive,clint.yaml. Please, indicate if > >> this should be changed. > >> > >> For the prior discussion see: > >> https://lore.kernel.org/all/20211015100941.17621-1-heinrich.schuchardt@canonical.com/ > >> https://lore.kernel.org/all/20211015120735.27972-1-heinrich.schuchardt@canonical.com/ > >> > >> A release candidate of the ACLINT specification is available at > >> https://github.com/riscv/riscv-aclint/releases > >> --- > >> .../bindings/timer/thead,clint.yaml | 62 +++++++++++++++++++ > >> 1 file changed, 62 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/timer/thead,clint.yaml > >> > >> diff --git a/Documentation/devicetree/bindings/timer/thead,clint.yaml b/Documentation/devicetree/bindings/timer/thead,clint.yaml > >> new file mode 100644 > >> index 000000000000..02463fb2043a > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/timer/thead,clint.yaml > >> @@ -0,0 +1,62 @@ > >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > >> +%YAML 1.2 > >> +--- > >> +$id: http://devicetree.org/schemas/timer/thead,clint.yaml# > >> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >> + > >> +title: SiFive Core Local Interruptor > >> + > >> +maintainers: > >> + - Palmer Dabbelt <palmer@dabbelt.com> > >> + - Anup Patel <anup.patel@wdc.com> > >> + > >> +description: > >> + T-HEAD (and other RISC-V) SOCs include an implementation of the T-HEAD > >> + Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor > >> + interrupts. It directly connects to the timer and inter-processor interrupt > >> + lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local > >> + interrupt controller is the parent interrupt controller for CLINT device. > >> + The clock frequency of the CLINT is specified via "timebase-frequency" DT > >> + property of "/cpus" DT node. The "timebase-frequency" DT property is > >> + described in Documentation/devicetree/bindings/riscv/cpus.yaml > >> + > >> +properties: > >> + compatible: > >> + items: > >> + - const: > >> + - allwinner,sun20i-d1-clint > >> + - const: > >> + - thead,clint0 > >> + > >> + description: > >> + Should be "<vendor>,<chip>-clint" and "thead,clint<version>" for > >> + the T-HEAD derived CLINTs. > >> + Supported compatible strings are - > >> + "allwinner,sun20i-d1-clint" for the CLINT in the Allwinner D1 SoC > >> + and "thead,clint0" for the T-HEAD IP block with no chip > >> + integration tweaks. > > > > T-HEAD uses the same versioning as SiFive? If you use version numbers in > > compatible strings, the numbering needs to be documented and correlate > > back to the h/w design. See [1]. IP release numbers for FPGA IP for > > example. What it should not be is the binding author making up 0, 1, 2, > > etc. versions. > > The only publicly available information on the IP block is: > > https://github.com/T-head-Semi/openc906/blob/main/doc/%E7%8E%84%E9%93%81C906%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf > > Page 3 has a version number for the whole document. Chapter 9 does not > have any version number for the CLINT. So should we simply call the > block "thead,clint" without any version number? > > @Guo: do you have more information accessible? We didn't define the version of "thead,clint", and it belonged to the CPU implementation version. We usually use "thead,clint0" at first, and update it to "thead,clintX" when we update it. > > Best regards > > Heinrich > > > > > Rob > > > > [1] Documentation/devicetree/bindings/sifive/sifive-blocks-ip-versioning.txt > > > > -- > opensbi mailing list > opensbi@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/opensbi
diff --git a/Documentation/devicetree/bindings/timer/thead,clint.yaml b/Documentation/devicetree/bindings/timer/thead,clint.yaml new file mode 100644 index 000000000000..02463fb2043a --- /dev/null +++ b/Documentation/devicetree/bindings/timer/thead,clint.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/thead,clint.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive Core Local Interruptor + +maintainers: + - Palmer Dabbelt <palmer@dabbelt.com> + - Anup Patel <anup.patel@wdc.com> + +description: + T-HEAD (and other RISC-V) SOCs include an implementation of the T-HEAD + Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor + interrupts. It directly connects to the timer and inter-processor interrupt + lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local + interrupt controller is the parent interrupt controller for CLINT device. + The clock frequency of the CLINT is specified via "timebase-frequency" DT + property of "/cpus" DT node. The "timebase-frequency" DT property is + described in Documentation/devicetree/bindings/riscv/cpus.yaml + +properties: + compatible: + items: + - const: + - allwinner,sun20i-d1-clint + - const: + - thead,clint0 + + description: + Should be "<vendor>,<chip>-clint" and "thead,clint<version>" for + the T-HEAD derived CLINTs. + Supported compatible strings are - + "allwinner,sun20i-d1-clint" for the CLINT in the Allwinner D1 SoC + and "thead,clint0" for the T-HEAD IP block with no chip + integration tweaks. + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + timer@2000000 { + compatible = "allwinner,sun20i-d1-clint", "thead,clint0"; + interrupts-extended = <&cpu1intc 3 &cpu1intc 7 + &cpu2intc 3 &cpu2intc 7 + &cpu3intc 3 &cpu3intc 7 + &cpu4intc 3 &cpu4intc 7>; + reg = <0x2000000 0x10000>; + }; +...
The CLINT in the T-HEAD 9xx CPUs is similar to the SiFive CLINT but does not support 64bit mmio access to the MTIMER device. OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the restriction and the "sifive,cling0" compatible string. An OpenSBI patch suggested to use "reg-io-width = <4>;" as the reg-io-width property is generally used in the devicetree schema for such a condition. As the design is not SiFive based it is preferable to apply a compatible string identifying T-HEAD instead. Add a new yaml file describing the T-HEAD CLINT. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> --- @Palmer, @Anup I copied you as maintainers from sifive,clint.yaml. Please, indicate if this should be changed. For the prior discussion see: https://lore.kernel.org/all/20211015100941.17621-1-heinrich.schuchardt@canonical.com/ https://lore.kernel.org/all/20211015120735.27972-1-heinrich.schuchardt@canonical.com/ A release candidate of the ACLINT specification is available at https://github.com/riscv/riscv-aclint/releases --- .../bindings/timer/thead,clint.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/thead,clint.yaml