| Message ID | 20211102021233.215980-1-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] drm/i915/display: Exit PSR when doing async flips | expand |
On Mon, Nov 01, 2021 at 07:12:33PM -0700, José Roberto de Souza wrote: > Changing the buffer in the middle of the scanout then entering an > period of flip idleness will cause part of the previous buffer being > diplayed to user when PSR is enabled. > > So here disabling and scheduling activation after a few milliseconds > when async flip is enabled in the state. > > The async flip check that we had in PSR compute is not executed at > every flip so it was not doing anything useful and is also being > dropped here. > > v2: > - scheduling the PSR work in _intel_psr_post_plane_update() > > Cc: Karthik B S <karthik.b.s@intel.com> > Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index 9d589d471e335..e1338f5b2967c 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -731,12 +731,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, > return false; > } > > - if (crtc_state->uapi.async_flip) { > - drm_dbg_kms(&dev_priv->drm, > - "PSR2 sel fetch not enabled, async flip enabled\n"); > - return false; > - } > - > /* Wa_14010254185 Wa_14010103792 */ > if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { > drm_dbg_kms(&dev_priv->drm, > @@ -1780,6 +1774,9 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, > if (psr->enabled && needs_to_disable) > intel_psr_disable_locked(intel_dp); > > + if (psr->enabled && crtc_state->uapi.async_flip) > + intel_psr_exit(intel_dp); > + > mutex_unlock(&psr->lock); > } > } > @@ -1810,6 +1807,9 @@ static void _intel_psr_post_plane_update(const struct intel_atomic_state *state, > if (crtc_state->crc_enabled && psr->enabled) > psr_force_hw_tracking_exit(intel_dp); > > + if (psr->enabled && !psr->active && crtc_state->uapi.async_flip) > + schedule_work(&intel_dp->psr.work); Dunno if there's much point on doing this for every async flip. The expectation is more or less that more async flips will come in. So we should probably do this only when switching back to sync flips. > + > mutex_unlock(&psr->lock); > } > } > -- > 2.33.1
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 9d589d471e335..e1338f5b2967c 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -731,12 +731,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, return false; } - if (crtc_state->uapi.async_flip) { - drm_dbg_kms(&dev_priv->drm, - "PSR2 sel fetch not enabled, async flip enabled\n"); - return false; - } - /* Wa_14010254185 Wa_14010103792 */ if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { drm_dbg_kms(&dev_priv->drm, @@ -1780,6 +1774,9 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, if (psr->enabled && needs_to_disable) intel_psr_disable_locked(intel_dp); + if (psr->enabled && crtc_state->uapi.async_flip) + intel_psr_exit(intel_dp); + mutex_unlock(&psr->lock); } } @@ -1810,6 +1807,9 @@ static void _intel_psr_post_plane_update(const struct intel_atomic_state *state, if (crtc_state->crc_enabled && psr->enabled) psr_force_hw_tracking_exit(intel_dp); + if (psr->enabled && !psr->active && crtc_state->uapi.async_flip) + schedule_work(&intel_dp->psr.work); + mutex_unlock(&psr->lock); } }
Changing the buffer in the middle of the scanout then entering an period of flip idleness will cause part of the previous buffer being diplayed to user when PSR is enabled. So here disabling and scheduling activation after a few milliseconds when async flip is enabled in the state. The async flip check that we had in PSR compute is not executed at every flip so it was not doing anything useful and is also being dropped here. v2: - scheduling the PSR work in _intel_psr_post_plane_update() Cc: Karthik B S <karthik.b.s@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)