| Message ID | 20211015210041.16858-1-radhakrishna.sripada@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v9] drm/i915: Update memory bandwidth formulae | expand |
Replying to the right patch this time. From what the bspec says, the changes look good. Minor feedback below inline. With that change, Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of > Radhakrishna Sripada > Sent: Friday, October 15, 2021 2:01 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v9] drm/i915: Update memory bandwidth > formulae > > The formulae has been updated to include more variables. Make sure the > code carries the same. > > Bspec: 64631, 54023 > > v2: Make GEN11 follow the default route and fix calculation of > maxdebw(RK) > v3: Fix div by zero on default case > Correct indent for fallthrough(Jani) > v4: Fix div by zero on gen11. > v5: Fix 0 max_numchannels case > v6: > - Split gen11/gen12 algorithms > - Fix RKL deburst value > - Fix difference b/ween ICL and TGL algorithms > - Protect deinterleave from being 0 > - Warn when numchannels exceeds max_numchannels > - Fix scaling of clk_max from different units > - s/deinterleave/channelwidth/ in calculating peakbw > - Fix off by one for num_planes TGL+ > - Fix SAGV check > v7: Fix div by zero error on gen11 > v8: Even though the algorithm for gen11 says that we need to return > derated bw for a qgv point whose planes are less than no of active > planes, we return 0 for deratedbw when only one plane is allowed. > We modify the algorithm to accommodate the case where no of active > planes are same as the min no of planes supported by a qgv point. > v9: Fix dclk scaling for dg1 > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Suggested-by: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > --- > drivers/gpu/drm/i915/display/intel_bw.c | 211 ++++++++++++++++++++---- > 1 file changed, 179 insertions(+), 32 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c > b/drivers/gpu/drm/i915/display/intel_bw.c > index 8d9d888e9316..15c006194c85 100644 > --- a/drivers/gpu/drm/i915/display/intel_bw.c > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > @@ -27,6 +27,9 @@ struct intel_qgv_info { > u8 num_points; > u8 num_psf_points; > u8 t_bl; > + u8 max_numchannels; > + u8 channel_width; > + u8 deinterleave; > }; > > static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private > *dev_priv, @@ -42,7 +45,7 @@ static int > dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv, > dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */ > else > dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */ > - sp->dclk = dclk_ratio * dclk_reference; > + sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + > 500, > +1000); > > val = intel_uncore_read(&dev_priv->uncore, > SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); > if (val & DG1_GEAR_TYPE) > @@ -69,6 +72,7 @@ static int icl_pcode_read_qgv_point_info(struct > drm_i915_private *dev_priv, > int point) > { > u32 val = 0, val2 = 0; > + u16 dclk; > int ret; > > ret = sandybridge_pcode_read(dev_priv, @@ -78,7 +82,8 @@ static > int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv, > if (ret) > return ret; > > - sp->dclk = val & 0xffff; > + dclk = val & 0xffff; > + sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) > > 11 ? > +500 : 0), 1000); > sp->t_rp = (val & 0xff0000) >> 16; > sp->t_rcd = (val & 0xff000000) >> 24; > > @@ -133,7 +138,8 @@ int icl_pcode_restrict_qgv_points(struct > drm_i915_private *dev_priv, } > > static int icl_get_qgv_points(struct drm_i915_private *dev_priv, > - struct intel_qgv_info *qi) > + struct intel_qgv_info *qi, > + bool is_y_tile) > { > const struct dram_info *dram_info = &dev_priv->dram_info; > int i, ret; > @@ -144,17 +150,41 @@ static int icl_get_qgv_points(struct > drm_i915_private *dev_priv, > if (DISPLAY_VER(dev_priv) == 12) > switch (dram_info->type) { > case INTEL_DRAM_DDR4: > - qi->t_bl = 4; > + qi->t_bl = is_y_tile ? 8 : 4; > + qi->max_numchannels = 2; > + qi->channel_width = 64; > + qi->deinterleave = is_y_tile ? 1 : 2; > break; > case INTEL_DRAM_DDR5: > - qi->t_bl = 8; > + qi->t_bl = is_y_tile ? 16 : 8; > + qi->max_numchannels = 4; > + qi->channel_width = 32; > + qi->deinterleave = is_y_tile ? 1 : 2; > + break; > + case INTEL_DRAM_LPDDR4: > + if (IS_ROCKETLAKE(dev_priv)) { > + qi->t_bl = 8; > + qi->max_numchannels = 4; > + qi->channel_width = 32; > + qi->deinterleave = 2; > + break; > + } > + fallthrough; > + case INTEL_DRAM_LPDDR5: > + qi->t_bl = 16; > + qi->max_numchannels = 8; > + qi->channel_width = 16; > + qi->deinterleave = is_y_tile ? 2 : 4; > break; > default: > qi->t_bl = 16; > + qi->max_numchannels = 1; > break; > } > - else if (DISPLAY_VER(dev_priv) == 11) > + else if (DISPLAY_VER(dev_priv) == 11) { > qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? > 4 : 8; > + qi->max_numchannels = 1; > + } > > if (drm_WARN_ON(&dev_priv->drm, > qi->num_points > ARRAY_SIZE(qi->points))) @@ - > 193,12 +223,6 @@ static int icl_get_qgv_points(struct drm_i915_private > *dev_priv, > return 0; > } > > -static int icl_calc_bw(int dclk, int num, int den) -{ > - /* multiples of 16.666MHz (100/6) */ > - return DIV_ROUND_CLOSEST(num * dclk * 100, den * 6); > -} > - > static int adl_calc_psf_bw(int clk) > { > /* > @@ -240,7 +264,7 @@ static const struct intel_sa_info tgl_sa_info = { }; > > static const struct intel_sa_info rkl_sa_info = { > - .deburst = 16, > + .deburst = 8, > .deprogbwlimit = 20, /* GB/s */ > .displayrtids = 128, > .derating = 10, > @@ -265,35 +289,130 @@ static int icl_get_bw_info(struct drm_i915_private > *dev_priv, const struct intel > struct intel_qgv_info qi = {}; > bool is_y_tile = true; /* assume y tile may be used */ > int num_channels = max_t(u8, 1, dev_priv- > >dram_info.num_channels); > - int deinterleave; > - int ipqdepth, ipqdepthpch; > + int ipqdepth, ipqdepthpch = 16; > int dclk_max; > int maxdebw; > + int num_groups = ARRAY_SIZE(dev_priv->max_bw); > int i, ret; > > - ret = icl_get_qgv_points(dev_priv, &qi); > + ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile); > if (ret) { > drm_dbg_kms(&dev_priv->drm, > "Failed to get memory subsystem information, > ignoring bandwidth limits"); > return ret; > } > > - deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2); > dclk_max = icl_sagv_max_dclk(&qi); > + maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10); > + ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels); > + qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2); > + > + for (i = 0; i < num_groups; i++) { > + struct intel_bw_info *bi = &dev_priv->max_bw[i]; > + int clpchgroup; > + int j; > + > + clpchgroup = (sa->deburst * qi.deinterleave / num_channels) > << i; > + bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1; > + > + bi->num_qgv_points = qi.num_points; > + bi->num_psf_gv_points = qi.num_psf_points; > + > + for (j = 0; j < qi.num_points; j++) { The j here can be more descriptive to make it easy to understand. s/j/sagv probably? Thanks, Anusha > + const struct intel_qgv_point *sp = &qi.points[j]; > + int ct, bw; > + > + /* > + * Max row cycle time > + * > + * FIXME what is the logic behind the > + * assumed burst length? > + */ > + ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd + > + (clpchgroup - 1) * qi.t_bl + sp->t_rdpre); > + bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * > num_channels, ct); > > - ipqdepthpch = 16; > + bi->deratedbw[j] = min(maxdebw, > + bw * (100 - sa->derating) / 100); > + > + drm_dbg_kms(&dev_priv->drm, > + "BW%d / QGV %d: num_planes=%d > deratedbw=%u\n", > + i, j, bi->num_planes, bi->deratedbw[j]); > + } > + } > + /* > + * In case if SAGV is disabled in BIOS, we always get 1 > + * SAGV point, but we can't send PCode commands to restrict it > + * as it will fail and pointless anyway. > + */ > + if (qi.num_points == 1) > + dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; > + else > + dev_priv->sagv_status = I915_SAGV_ENABLED; > + > + return 0; > +} > + > +static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const > +struct intel_sa_info *sa) { > + struct intel_qgv_info qi = {}; > + const struct dram_info *dram_info = &dev_priv->dram_info; > + bool is_y_tile = true; /* assume y tile may be used */ > + int num_channels = max_t(u8, 1, dev_priv- > >dram_info.num_channels); > + int ipqdepth, ipqdepthpch = 16; > + int dclk_max; > + int maxdebw, peakbw; > + int clperchgroup; > + int num_groups = ARRAY_SIZE(dev_priv->max_bw); > + int i, ret; > + > + ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile); > + if (ret) { > + drm_dbg_kms(&dev_priv->drm, > + "Failed to get memory subsystem information, > ignoring bandwidth limits"); > + return ret; > + } > + > + if (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == > INTEL_DRAM_LPDDR5) > + num_channels *= 2; > + > + qi.deinterleave = qi.deinterleave ? : DIV_ROUND_UP(num_channels, > +is_y_tile ? 4 : 2); > + > + if (num_channels < qi.max_numchannels && DISPLAY_VER(dev_priv) > >= 12) > + qi.deinterleave = max(DIV_ROUND_UP(qi.deinterleave, 2), 1); > + > + if (DISPLAY_VER(dev_priv) > 11 && num_channels > > qi.max_numchannels) > + drm_warn(&dev_priv->drm, "Number of channels exceeds > max number of channels."); > + if (qi.max_numchannels != 0) > + num_channels = min_t(u8, num_channels, > qi.max_numchannels); > + > + dclk_max = icl_sagv_max_dclk(&qi); > + > + peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * > dclk_max; > + maxdebw = min(sa->deprogbwlimit * 1000, peakbw * 6 / 10); /* 60% > */ > > - maxdebw = min(sa->deprogbwlimit * 1000, > - icl_calc_bw(dclk_max, 16, 1) * 6 / 10); /* 60% */ > ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels); > + /* > + * clperchgroup = 4kpagespermempage * clperchperblock, > + * clperchperblock = 8 / num_channels * interleave > + */ > + clperchgroup = 4 * DIV_ROUND_UP(8, num_channels) * > qi.deinterleave; > > - for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) { > + for (i = 0; i < num_groups; i++) { > struct intel_bw_info *bi = &dev_priv->max_bw[i]; > + struct intel_bw_info *bi_next; > int clpchgroup; > int j; > > - clpchgroup = (sa->deburst * deinterleave / num_channels) << > i; > - bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1; > + if (i < num_groups - 1) > + bi_next = &dev_priv->max_bw[i + 1]; > + > + clpchgroup = (sa->deburst * qi.deinterleave / num_channels) > << i; > + > + if (i < num_groups - 1 && clpchgroup < clperchgroup) > + bi_next->num_planes = (ipqdepth - clpchgroup) / > clpchgroup + 1; > + else > + bi_next->num_planes = 0; > > bi->num_qgv_points = qi.num_points; > bi->num_psf_gv_points = qi.num_psf_points; @@ -310,7 > +429,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, > const struct intel > */ > ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd + > (clpchgroup - 1) * qi.t_bl + sp->t_rdpre); > - bw = icl_calc_bw(sp->dclk, clpchgroup * 32 * > num_channels, ct); > + bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * > num_channels, ct); > > bi->deratedbw[j] = min(maxdebw, > bw * (100 - sa->derating) / 100); > @@ -329,9 +448,6 @@ static int icl_get_bw_info(struct drm_i915_private > *dev_priv, const struct intel > "BW%d / PSF GV %d: num_planes=%d > bw=%u\n", > i, j, bi->num_planes, bi->psf_bw[j]); > } > - > - if (bi->num_planes == 1) > - break; > } > > /* > @@ -395,6 +511,34 @@ static unsigned int icl_max_bw(struct > drm_i915_private *dev_priv, > return 0; > } > > +static unsigned int tgl_max_bw(struct drm_i915_private *dev_priv, > + int num_planes, int qgv_point) { > + int i; > + > + /* > + * Let's return max bw for 0 planes > + */ > + num_planes = max(1, num_planes); > + > + for (i = ARRAY_SIZE(dev_priv->max_bw) - 1; i >= 0; i--) { > + const struct intel_bw_info *bi = > + &dev_priv->max_bw[i]; > + > + /* > + * Pcode will not expose all QGV points when > + * SAGV is forced to off/min/med/max. > + */ > + if (qgv_point >= bi->num_qgv_points) > + return UINT_MAX; > + > + if (num_planes <= bi->num_planes) > + return bi->deratedbw[qgv_point]; > + } > + > + return dev_priv->max_bw[0].deratedbw[qgv_point]; > +} > + > static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv, > int psf_gv_point) > { > @@ -412,13 +556,13 @@ void intel_bw_init_hw(struct drm_i915_private > *dev_priv) > if (IS_DG2(dev_priv)) > dg2_get_bw_info(dev_priv); > else if (IS_ALDERLAKE_P(dev_priv)) > - icl_get_bw_info(dev_priv, &adlp_sa_info); > + tgl_get_bw_info(dev_priv, &adlp_sa_info); > else if (IS_ALDERLAKE_S(dev_priv)) > - icl_get_bw_info(dev_priv, &adls_sa_info); > + tgl_get_bw_info(dev_priv, &adls_sa_info); > else if (IS_ROCKETLAKE(dev_priv)) > - icl_get_bw_info(dev_priv, &rkl_sa_info); > + tgl_get_bw_info(dev_priv, &rkl_sa_info); > else if (DISPLAY_VER(dev_priv) == 12) > - icl_get_bw_info(dev_priv, &tgl_sa_info); > + tgl_get_bw_info(dev_priv, &tgl_sa_info); > else if (DISPLAY_VER(dev_priv) == 11) > icl_get_bw_info(dev_priv, &icl_sa_info); } @@ -746,7 > +890,10 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) > for (i = 0; i < num_qgv_points; i++) { > unsigned int max_data_rate; > > - max_data_rate = icl_max_bw(dev_priv, num_active_planes, > i); > + if (DISPLAY_VER(dev_priv) > 11) > + max_data_rate = tgl_max_bw(dev_priv, > num_active_planes, i); > + else > + max_data_rate = icl_max_bw(dev_priv, > num_active_planes, i); > /* > * We need to know which qgv point gives us > * maximum bandwidth in order to disable SAGV > -- > 2.20.1
> -----Original Message----- > From: Srivatsa, Anusha <anusha.srivatsa@intel.com> > Sent: Thursday, October 28, 2021 2:04 PM > To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; intel- > gfx@lists.freedesktop.org > Subject: RE: [Intel-gfx] [PATCH v9] drm/i915: Update memory bandwidth > formulae > > Replying to the right patch this time. > From what the bspec says, the changes look good. > Minor feedback below inline. > > With that change, > Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > > > > -----Original Message----- > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of > > Radhakrishna Sripada > > Sent: Friday, October 15, 2021 2:01 PM > > To: intel-gfx@lists.freedesktop.org > > Subject: [Intel-gfx] [PATCH v9] drm/i915: Update memory bandwidth > > formulae > > > > The formulae has been updated to include more variables. Make sure the > > code carries the same. > > > > Bspec: 64631, 54023 > > > > v2: Make GEN11 follow the default route and fix calculation of > > maxdebw(RK) > > v3: Fix div by zero on default case > > Correct indent for fallthrough(Jani) > > v4: Fix div by zero on gen11. > > v5: Fix 0 max_numchannels case > > v6: > > - Split gen11/gen12 algorithms > > - Fix RKL deburst value > > - Fix difference b/ween ICL and TGL algorithms > > - Protect deinterleave from being 0 > > - Warn when numchannels exceeds max_numchannels > > - Fix scaling of clk_max from different units > > - s/deinterleave/channelwidth/ in calculating peakbw > > - Fix off by one for num_planes TGL+ > > - Fix SAGV check > > v7: Fix div by zero error on gen11 > > v8: Even though the algorithm for gen11 says that we need to return > > derated bw for a qgv point whose planes are less than no of active > > planes, we return 0 for deratedbw when only one plane is allowed. > > We modify the algorithm to accommodate the case where no of active > > planes are same as the min no of planes supported by a qgv point. > > v9: Fix dclk scaling for dg1 > > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Suggested-by: Matt Roper <matthew.d.roper@intel.com> > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_bw.c | 211 ++++++++++++++++++++---- > > 1 file changed, 179 insertions(+), 32 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c > > b/drivers/gpu/drm/i915/display/intel_bw.c > > index 8d9d888e9316..15c006194c85 100644 > > --- a/drivers/gpu/drm/i915/display/intel_bw.c > > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > > @@ -27,6 +27,9 @@ struct intel_qgv_info { > > u8 num_points; > > u8 num_psf_points; > > u8 t_bl; > > + u8 max_numchannels; > > + u8 channel_width; > > + u8 deinterleave; > > }; > > > > static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private > > *dev_priv, @@ -42,7 +45,7 @@ static int > > dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv, > > dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */ > > else > > dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */ > > - sp->dclk = dclk_ratio * dclk_reference; > > + sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + > > 500, > > +1000); > > > > val = intel_uncore_read(&dev_priv->uncore, > > SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); > > if (val & DG1_GEAR_TYPE) > > @@ -69,6 +72,7 @@ static int icl_pcode_read_qgv_point_info(struct > > drm_i915_private *dev_priv, > > int point) > > { > > u32 val = 0, val2 = 0; > > + u16 dclk; > > int ret; > > > > ret = sandybridge_pcode_read(dev_priv, @@ -78,7 +82,8 @@ static > > int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv, > > if (ret) > > return ret; > > > > - sp->dclk = val & 0xffff; > > + dclk = val & 0xffff; > > + sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) > > > 11 ? > > +500 : 0), 1000); > > sp->t_rp = (val & 0xff0000) >> 16; > > sp->t_rcd = (val & 0xff000000) >> 24; > > > > @@ -133,7 +138,8 @@ int icl_pcode_restrict_qgv_points(struct > > drm_i915_private *dev_priv, } > > > > static int icl_get_qgv_points(struct drm_i915_private *dev_priv, > > - struct intel_qgv_info *qi) > > + struct intel_qgv_info *qi, > > + bool is_y_tile) > > { > > const struct dram_info *dram_info = &dev_priv->dram_info; > > int i, ret; > > @@ -144,17 +150,41 @@ static int icl_get_qgv_points(struct > > drm_i915_private *dev_priv, > > if (DISPLAY_VER(dev_priv) == 12) > > switch (dram_info->type) { > > case INTEL_DRAM_DDR4: > > - qi->t_bl = 4; > > + qi->t_bl = is_y_tile ? 8 : 4; > > + qi->max_numchannels = 2; > > + qi->channel_width = 64; > > + qi->deinterleave = is_y_tile ? 1 : 2; > > break; > > case INTEL_DRAM_DDR5: > > - qi->t_bl = 8; > > + qi->t_bl = is_y_tile ? 16 : 8; > > + qi->max_numchannels = 4; > > + qi->channel_width = 32; > > + qi->deinterleave = is_y_tile ? 1 : 2; > > + break; > > + case INTEL_DRAM_LPDDR4: > > + if (IS_ROCKETLAKE(dev_priv)) { > > + qi->t_bl = 8; > > + qi->max_numchannels = 4; > > + qi->channel_width = 32; > > + qi->deinterleave = 2; > > + break; > > + } > > + fallthrough; > > + case INTEL_DRAM_LPDDR5: > > + qi->t_bl = 16; > > + qi->max_numchannels = 8; > > + qi->channel_width = 16; > > + qi->deinterleave = is_y_tile ? 2 : 4; > > break; > > default: > > qi->t_bl = 16; > > + qi->max_numchannels = 1; > > break; > > } > > - else if (DISPLAY_VER(dev_priv) == 11) > > + else if (DISPLAY_VER(dev_priv) == 11) { > > qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? > > 4 : 8; > > + qi->max_numchannels = 1; > > + } > > > > if (drm_WARN_ON(&dev_priv->drm, > > qi->num_points > ARRAY_SIZE(qi->points))) @@ - > > 193,12 +223,6 @@ static int icl_get_qgv_points(struct drm_i915_private > > *dev_priv, > > return 0; > > } > > > > -static int icl_calc_bw(int dclk, int num, int den) -{ > > - /* multiples of 16.666MHz (100/6) */ > > - return DIV_ROUND_CLOSEST(num * dclk * 100, den * 6); > > -} > > - > > static int adl_calc_psf_bw(int clk) > > { > > /* > > @@ -240,7 +264,7 @@ static const struct intel_sa_info tgl_sa_info = { }; > > > > static const struct intel_sa_info rkl_sa_info = { > > - .deburst = 16, > > + .deburst = 8, > > .deprogbwlimit = 20, /* GB/s */ > > .displayrtids = 128, > > .derating = 10, > > @@ -265,35 +289,130 @@ static int icl_get_bw_info(struct drm_i915_private > > *dev_priv, const struct intel > > struct intel_qgv_info qi = {}; > > bool is_y_tile = true; /* assume y tile may be used */ > > int num_channels = max_t(u8, 1, dev_priv- > > >dram_info.num_channels); > > - int deinterleave; > > - int ipqdepth, ipqdepthpch; > > + int ipqdepth, ipqdepthpch = 16; > > int dclk_max; > > int maxdebw; > > + int num_groups = ARRAY_SIZE(dev_priv->max_bw); > > int i, ret; > > > > - ret = icl_get_qgv_points(dev_priv, &qi); > > + ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile); > > if (ret) { > > drm_dbg_kms(&dev_priv->drm, > > "Failed to get memory subsystem information, > > ignoring bandwidth limits"); > > return ret; > > } > > > > - deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2); > > dclk_max = icl_sagv_max_dclk(&qi); > > + maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10); > > + ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels); > > + qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2); > > + > > + for (i = 0; i < num_groups; i++) { > > + struct intel_bw_info *bi = &dev_priv->max_bw[i]; > > + int clpchgroup; > > + int j; > > + > > + clpchgroup = (sa->deburst * qi.deinterleave / num_channels) > > << i; > > + bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1; > > + > > + bi->num_qgv_points = qi.num_points; > > + bi->num_psf_gv_points = qi.num_psf_points; > > + > > + for (j = 0; j < qi.num_points; j++) { > The j here can be more descriptive to make it easy to understand. s/j/sagv > probably? I am not sure if this case warrants a departure from standard convention of naming iterators. This iterator j is used in the current version of the code and I am skeptical about changing it. Thanks for the review, Radhakrishna(RK) Sripada > > Thanks, > Anusha > > + const struct intel_qgv_point *sp = &qi.points[j]; > > + int ct, bw; > > + > > + /* > > + * Max row cycle time > > + * > > + * FIXME what is the logic behind the > > + * assumed burst length? > > + */ > > + ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd + > > + (clpchgroup - 1) * qi.t_bl + sp->t_rdpre); > > + bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * > > num_channels, ct); > > > > - ipqdepthpch = 16; > > + bi->deratedbw[j] = min(maxdebw, > > + bw * (100 - sa->derating) / 100); > > + > > + drm_dbg_kms(&dev_priv->drm, > > + "BW%d / QGV %d: num_planes=%d > > deratedbw=%u\n", > > + i, j, bi->num_planes, bi->deratedbw[j]); > > + } > > + } > > + /* > > + * In case if SAGV is disabled in BIOS, we always get 1 > > + * SAGV point, but we can't send PCode commands to restrict it > > + * as it will fail and pointless anyway. > > + */ > > + if (qi.num_points == 1) > > + dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; > > + else > > + dev_priv->sagv_status = I915_SAGV_ENABLED; > > + > > + return 0; > > +} > > + > > +static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const > > +struct intel_sa_info *sa) { > > + struct intel_qgv_info qi = {}; > > + const struct dram_info *dram_info = &dev_priv->dram_info; > > + bool is_y_tile = true; /* assume y tile may be used */ > > + int num_channels = max_t(u8, 1, dev_priv- > > >dram_info.num_channels); > > + int ipqdepth, ipqdepthpch = 16; > > + int dclk_max; > > + int maxdebw, peakbw; > > + int clperchgroup; > > + int num_groups = ARRAY_SIZE(dev_priv->max_bw); > > + int i, ret; > > + > > + ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile); > > + if (ret) { > > + drm_dbg_kms(&dev_priv->drm, > > + "Failed to get memory subsystem information, > > ignoring bandwidth limits"); > > + return ret; > > + } > > + > > + if (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == > > INTEL_DRAM_LPDDR5) > > + num_channels *= 2; > > + > > + qi.deinterleave = qi.deinterleave ? : DIV_ROUND_UP(num_channels, > > +is_y_tile ? 4 : 2); > > + > > + if (num_channels < qi.max_numchannels && DISPLAY_VER(dev_priv) > > >= 12) > > + qi.deinterleave = max(DIV_ROUND_UP(qi.deinterleave, 2), 1); > > + > > + if (DISPLAY_VER(dev_priv) > 11 && num_channels > > > qi.max_numchannels) > > + drm_warn(&dev_priv->drm, "Number of channels exceeds > > max number of channels."); > > + if (qi.max_numchannels != 0) > > + num_channels = min_t(u8, num_channels, > > qi.max_numchannels); > > + > > + dclk_max = icl_sagv_max_dclk(&qi); > > + > > + peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * > > dclk_max; > > + maxdebw = min(sa->deprogbwlimit * 1000, peakbw * 6 / 10); /* 60% > > */ > > > > - maxdebw = min(sa->deprogbwlimit * 1000, > > - icl_calc_bw(dclk_max, 16, 1) * 6 / 10); /* 60% */ > > ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels); > > + /* > > + * clperchgroup = 4kpagespermempage * clperchperblock, > > + * clperchperblock = 8 / num_channels * interleave > > + */ > > + clperchgroup = 4 * DIV_ROUND_UP(8, num_channels) * > > qi.deinterleave; > > > > - for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) { > > + for (i = 0; i < num_groups; i++) { > > struct intel_bw_info *bi = &dev_priv->max_bw[i]; > > + struct intel_bw_info *bi_next; > > int clpchgroup; > > int j; > > > > - clpchgroup = (sa->deburst * deinterleave / num_channels) << > > i; > > - bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1; > > + if (i < num_groups - 1) > > + bi_next = &dev_priv->max_bw[i + 1]; > > + > > + clpchgroup = (sa->deburst * qi.deinterleave / num_channels) > > << i; > > + > > + if (i < num_groups - 1 && clpchgroup < clperchgroup) > > + bi_next->num_planes = (ipqdepth - clpchgroup) / > > clpchgroup + 1; > > + else > > + bi_next->num_planes = 0; > > > > bi->num_qgv_points = qi.num_points; > > bi->num_psf_gv_points = qi.num_psf_points; @@ -310,7 > > +429,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, > > const struct intel > > */ > > ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd + > > (clpchgroup - 1) * qi.t_bl + sp->t_rdpre); > > - bw = icl_calc_bw(sp->dclk, clpchgroup * 32 * > > num_channels, ct); > > + bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * > > num_channels, ct); > > > > bi->deratedbw[j] = min(maxdebw, > > bw * (100 - sa->derating) / 100); > > @@ -329,9 +448,6 @@ static int icl_get_bw_info(struct drm_i915_private > > *dev_priv, const struct intel > > "BW%d / PSF GV %d: num_planes=%d > > bw=%u\n", > > i, j, bi->num_planes, bi->psf_bw[j]); > > } > > - > > - if (bi->num_planes == 1) > > - break; > > } > > > > /* > > @@ -395,6 +511,34 @@ static unsigned int icl_max_bw(struct > > drm_i915_private *dev_priv, > > return 0; > > } > > > > +static unsigned int tgl_max_bw(struct drm_i915_private *dev_priv, > > + int num_planes, int qgv_point) { > > + int i; > > + > > + /* > > + * Let's return max bw for 0 planes > > + */ > > + num_planes = max(1, num_planes); > > + > > + for (i = ARRAY_SIZE(dev_priv->max_bw) - 1; i >= 0; i--) { > > + const struct intel_bw_info *bi = > > + &dev_priv->max_bw[i]; > > + > > + /* > > + * Pcode will not expose all QGV points when > > + * SAGV is forced to off/min/med/max. > > + */ > > + if (qgv_point >= bi->num_qgv_points) > > + return UINT_MAX; > > + > > + if (num_planes <= bi->num_planes) > > + return bi->deratedbw[qgv_point]; > > + } > > + > > + return dev_priv->max_bw[0].deratedbw[qgv_point]; > > +} > > + > > static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv, > > int psf_gv_point) > > { > > @@ -412,13 +556,13 @@ void intel_bw_init_hw(struct drm_i915_private > > *dev_priv) > > if (IS_DG2(dev_priv)) > > dg2_get_bw_info(dev_priv); > > else if (IS_ALDERLAKE_P(dev_priv)) > > - icl_get_bw_info(dev_priv, &adlp_sa_info); > > + tgl_get_bw_info(dev_priv, &adlp_sa_info); > > else if (IS_ALDERLAKE_S(dev_priv)) > > - icl_get_bw_info(dev_priv, &adls_sa_info); > > + tgl_get_bw_info(dev_priv, &adls_sa_info); > > else if (IS_ROCKETLAKE(dev_priv)) > > - icl_get_bw_info(dev_priv, &rkl_sa_info); > > + tgl_get_bw_info(dev_priv, &rkl_sa_info); > > else if (DISPLAY_VER(dev_priv) == 12) > > - icl_get_bw_info(dev_priv, &tgl_sa_info); > > + tgl_get_bw_info(dev_priv, &tgl_sa_info); > > else if (DISPLAY_VER(dev_priv) == 11) > > icl_get_bw_info(dev_priv, &icl_sa_info); } @@ -746,7 > > +890,10 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) > > for (i = 0; i < num_qgv_points; i++) { > > unsigned int max_data_rate; > > > > - max_data_rate = icl_max_bw(dev_priv, num_active_planes, > > i); > > + if (DISPLAY_VER(dev_priv) > 11) > > + max_data_rate = tgl_max_bw(dev_priv, > > num_active_planes, i); > > + else > > + max_data_rate = icl_max_bw(dev_priv, > > num_active_planes, i); > > /* > > * We need to know which qgv point gives us > > * maximum bandwidth in order to disable SAGV > > -- > > 2.20.1
From: Patchwork <patchwork@emeril.freedesktop.org>
Sent: Friday, October 15, 2021 6:48 PM
To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for drm/i915: Update memory bandwidth formulae (rev9)
Patch Details
Series:
drm/i915: Update memory bandwidth formulae (rev9)
URL:
https://patchwork.freedesktop.org/series/95138/
State:
failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/index.html
CI Bug Log - changes from CI_DRM_10744_full -> Patchwork_21357_full
Summary
FAILURE
Serious unknown changes coming with Patchwork_21357_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21357_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
Here are the unknown changes that may have been introduced in Patchwork_21357_full:
IGT changes
Possible regressions
* igt@kms_bw@linear-tiling-6-displays-3840x2160p:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb5/igt@kms_bw@linear-tiling-6-displays-3840x2160p.html>
RK: This test looks flaky and has failed across multiple platforms. The error does not indicate issue wrt bw calculations and
can be ignored.
Thanks,
Radhakrishna Sripada
Warnings
* igt@runner@aborted:
* shard-iclb: (FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb3/igt@runner@aborted.html>, FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb4/igt@runner@aborted.html>, FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb6/igt@runner@aborted.html>, FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb4/igt@runner@aborted.html>, FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb8/igt@runner@aborted.html>, FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb5/igt@runner@aborted.html>) ([i915#3002] / [i915#4006]) -> (FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb1/igt@runner@aborted.html>, FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb4/igt@runner@aborted.html>, FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb5/igt@runner@aborted.html>, FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb5/igt@runner@aborted.html>, FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb7/igt@runner@aborted.html>) ([i915#3002])
Known issues
Here are the changes found in Patchwork_21357_full that come from known issues:
IGT changes
Issues hit
* igt@gem_create@create-massive:
* shard-apl: NOTRUN -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl6/igt@gem_create@create-massive.html> ([i915#3002])
* igt@gem_ctx_persistence@engines-hang:
* shard-snb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-snb5/igt@gem_ctx_persistence@engines-hang.html> ([fdo#109271] / [i915#1099])
* igt@gem_ctx_sseu@invalid-args:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@gem_ctx_sseu@invalid-args.html> ([i915#280])
* igt@gem_exec_fair@basic-none-solo@rcs0:
* shard-kbl: NOTRUN -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl6/igt@gem_exec_fair@basic-none-solo@rcs0.html> ([i915#2842])
* igt@gem_exec_fair@basic-none-vip@rcs0:
* shard-kbl: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-kbl1/igt@gem_exec_fair@basic-none-vip@rcs0.html> -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl4/igt@gem_exec_fair@basic-none-vip@rcs0.html> ([i915#2842])
* igt@gem_exec_fair@basic-pace-share@rcs0:
* shard-tglb: NOTRUN -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html> ([i915#2842])
* igt@gem_exec_fair@basic-pace-solo@rcs0:
* shard-glk: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-glk1/igt@gem_exec_fair@basic-pace-solo@rcs0.html> -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-glk1/igt@gem_exec_fair@basic-pace-solo@rcs0.html> ([i915#2842]) +1 similar issue
* igt@gem_exec_params@no-bsd:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb3/igt@gem_exec_params@no-bsd.html> ([fdo#109283])
* igt@gem_pread@exhaustion:
* shard-apl: NOTRUN -> WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl1/igt@gem_pread@exhaustion.html> ([i915#2658])
* shard-kbl: NOTRUN -> WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl6/igt@gem_pread@exhaustion.html> ([i915#2658])
* igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb1/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html> ([i915#4270])
* igt@gem_softpin@allocator-basic-reserve:
* shard-skl: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-skl7/igt@gem_softpin@allocator-basic-reserve.html> -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl8/igt@gem_softpin@allocator-basic-reserve.html> ([i915#1982])
* igt@gem_userptr_blits@create-destroy-unsync:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb1/igt@gem_userptr_blits@create-destroy-unsync.html> ([i915#3297])
* igt@gem_userptr_blits@input-checking:
* shard-skl: NOTRUN -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl10/igt@gem_userptr_blits@input-checking.html> ([i915#3002])
* igt@gen3_render_tiledy_blits:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@gen3_render_tiledy_blits.html> ([fdo#109289])
* igt@gen9_exec_parse@basic-rejected:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb3/igt@gen9_exec_parse@basic-rejected.html> ([i915#2856])
* igt@gen9_exec_parse@unaligned-access:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@gen9_exec_parse@unaligned-access.html> ([i915#2856])
* igt@kms_big_fb@linear-32bpp-rotate-0:
* shard-glk: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-glk7/igt@kms_big_fb@linear-32bpp-rotate-0.html> -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-glk5/igt@kms_big_fb@linear-32bpp-rotate-0.html> ([i915#118])
* igt@kms_big_fb@x-tiled-16bpp-rotate-90:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb2/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html> ([fdo#111614]) +1 similar issue
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
* shard-kbl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html> ([fdo#109271] / [i915#3777]) +1 similar issue
* shard-apl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html> ([fdo#109271] / [i915#3777]) +1 similar issue
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
* shard-skl: NOTRUN -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl10/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html> ([i915#3722])
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html> ([fdo#111615])
* igt@kms_big_joiner@basic:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@kms_big_joiner@basic.html> ([i915#2705])
* igt@kms_bw@linear-tiling-4-displays-3840x2160p:
* shard-tglb: NOTRUN -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_bw@linear-tiling-4-displays-3840x2160p.html> ([i915#1385])
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html> ([fdo#109278] / [i915#3886])
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
* shard-skl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl1/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html> ([fdo#109271] / [i915#3886])
* igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs:
* shard-snb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-snb5/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs.html> ([fdo#109271]) +218 similar issues
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
* shard-kbl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl7/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html> ([fdo#109271] / [i915#3886]) +5 similar issues
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
* shard-apl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl3/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html> ([fdo#109271] / [i915#3886]) +8 similar issues
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb3/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html> ([i915#3689] / [i915#3886])
* igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs.html> ([fdo#109278]) +7 similar issues
* igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb1/igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs.html> ([i915#3689]) +1 similar issue
* igt@kms_chamelium@dp-edid-change-during-suspend:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@kms_chamelium@dp-edid-change-during-suspend.html> ([fdo#109284] / [fdo#111827]) +3 similar issues
* igt@kms_chamelium@hdmi-audio-edid:
* shard-kbl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl3/igt@kms_chamelium@hdmi-audio-edid.html> ([fdo#109271] / [fdo#111827]) +10 similar issues
* igt@kms_chamelium@vga-hpd:
* shard-apl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl2/igt@kms_chamelium@vga-hpd.html> ([fdo#109271] / [fdo#111827]) +19 similar issues
* igt@kms_chamelium@vga-hpd-for-each-pipe:
* shard-skl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl7/igt@kms_chamelium@vga-hpd-for-each-pipe.html> ([fdo#109271] / [fdo#111827]) +7 similar issues
* igt@kms_chamelium@vga-hpd-without-ddc:
* shard-snb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-snb5/igt@kms_chamelium@vga-hpd-without-ddc.html> ([fdo#109271] / [fdo#111827]) +11 similar issues
* igt@kms_color_chamelium@pipe-d-ctm-max:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb1/igt@kms_color_chamelium@pipe-d-ctm-max.html> ([fdo#109284] / [fdo#111827]) +7 similar issues
* igt@kms_content_protection@atomic:
* shard-kbl: NOTRUN -> TIMEOUT<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl6/igt@kms_content_protection@atomic.html> ([i915#1319]) +1 similar issue
* shard-apl: NOTRUN -> TIMEOUT<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl1/igt@kms_content_protection@atomic.html> ([i915#1319])
* igt@kms_content_protection@dp-mst-type-0:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_content_protection@dp-mst-type-0.html> ([i915#3116])
* igt@kms_content_protection@type1:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_content_protection@type1.html> ([fdo#111828])
* igt@kms_cursor_crc@pipe-a-cursor-512x512-onscreen:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_cursor_crc@pipe-a-cursor-512x512-onscreen.html> ([fdo#109279] / [i915#3359]) +2 similar issues
* igt@kms_cursor_crc@pipe-d-cursor-max-size-sliding:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-max-size-sliding.html> ([i915#3359]) +2 similar issues
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
* shard-glk: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html> -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html> ([i915#72])
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html> ([fdo#109274] / [fdo#109278])
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
* shard-skl: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html> -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html> ([i915#2346])
* igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2:
* shard-glk: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html> -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html> ([i915#79]) +1 similar issue
* igt@kms_flip@flip-vs-expired-vblank@a-dp1:
* shard-apl: NOTRUN -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl2/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html> ([i915#79])
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
* shard-skl: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html> -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html> ([i915#2122]) +1 similar issue
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html> ([i915#2587])
* igt@kms_frontbuffer_tracking@fbc-suspend:
* shard-kbl: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html> -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html> ([i915#180]) +2 similar issues
* igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt:
* shard-skl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl7/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt.html> ([fdo#109271]) +66 similar issues
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html> ([fdo#111825]) +16 similar issues
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render.html> ([fdo#109280]) +3 similar issues
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite:
* shard-apl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite.html> ([fdo#109271]) +204 similar issues
* igt@kms_hdr@static-toggle-dpms:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb2/igt@kms_hdr@static-toggle-dpms.html> ([i915#1187])
* igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html> ([fdo#109289])
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
* shard-apl: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html> -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html> ([i915#180]) +1 similar issue
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
* shard-tglb: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-tglb3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html> -> INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html> ([i915#456])
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
* shard-apl: NOTRUN -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html> ([fdo#108145] / [i915#265]) +3 similar issues
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
* shard-kbl: NOTRUN -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl6/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html> ([fdo#108145] / [i915#265])
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
* shard-skl: NOTRUN -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html> ([fdo#108145] / [i915#265])
* igt@kms_plane_lowres@pipe-b-tiling-y:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb3/igt@kms_plane_lowres@pipe-b-tiling-y.html> ([i915#3536])
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html> ([i915#2920]) +1 similar issue
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
* shard-kbl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html> ([fdo#109271] / [i915#658]) +2 similar issues
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
* shard-skl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl10/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html> ([fdo#109271] / [i915#658])
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
* shard-apl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl8/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html> ([fdo#109271] / [i915#658]) +1 similar issue
* igt@kms_psr@psr2_cursor_blt:
* shard-tglb: NOTRUN -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_psr@psr2_cursor_blt.html> ([i915#132] / [i915#3467])
* igt@kms_psr@psr2_cursor_mmap_cpu:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_cpu.html> ([fdo#109441])
* igt@kms_setmode@basic:
* shard-snb: NOTRUN -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-snb7/igt@kms_setmode@basic.html> ([i915#31])
* igt@kms_vblank@pipe-d-wait-idle:
* shard-kbl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl6/igt@kms_vblank@pipe-d-wait-idle.html> ([fdo#109271] / [i915#533]) +1 similar issue
* shard-apl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl1/igt@kms_vblank@pipe-d-wait-idle.html> ([fdo#109271] / [i915#533]) +1 similar issue
* igt@kms_writeback@writeback-check-output:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@kms_writeback@writeback-check-output.html> ([i915#2437])
* igt@kms_writeback@writeback-fb-id:
* shard-apl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl3/igt@kms_writeback@writeback-fb-id.html> ([fdo#109271] / [i915#2437]) +1 similar issue
* igt@nouveau_crc@ctx-flip-threshold-reset-after-capture:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@nouveau_crc@ctx-flip-threshold-reset-after-capture.html> ([i915#2530])
* igt@prime_nv_api@i915_nv_import_twice_check_flink_name:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb1/igt@prime_nv_api@i915_nv_import_twice_check_flink_name.html> ([fdo#109291]) +1 similar issue
* igt@prime_nv_pcopy@test2:
* shard-kbl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl6/igt@prime_nv_pcopy@test2.html> ([fdo#109271]) +113 similar issues
* igt@prime_nv_pcopy@test3_3:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@prime_nv_pcopy@test3_3.html> ([fdo#109291])
* igt@sysfs_clients@fair-7:
* shard-tglb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@sysfs_clients@fair-7.html> ([i915#2994])
* igt@sysfs_clients@pidname:
* shard-apl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl8/igt@sysfs_clients@pidname.html> ([fdo#109271] / [i915#2994]) +3 similar issues
* igt@sysfs_clients@split-25:
* shard-kbl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl6/igt@sysfs_clients@split-25.html> ([fdo#109271] / [i915#2994])
Possible fixes
* igt@gem_ctx_isolation@preservation-s3@bcs0:
* shard-tglb: INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-tglb7/igt@gem_ctx_isolation@preservation-s3@bcs0.html> ([i915#456]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb3/igt@gem_ctx_isolation@preservation-s3@bcs0.html>
* shard-kbl: DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html> ([i915#180]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@bcs0.html> +6 similar issues
* igt@gem_ctx_persistence@engines-hostile@vecs0:
* shard-kbl: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-kbl3/igt@gem_ctx_persistence@engines-hostile@vecs0.html> ([i915#2410]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl7/igt@gem_ctx_persistence@engines-hostile@vecs0.html>
* igt@gem_exec_fair@basic-pace@vecs0:
* shard-glk: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-glk4/igt@gem_exec_fair@basic-pace@vecs0.html> ([i915#2842]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-glk6/igt@gem_exec_fair@basic-pace@vecs0.html>
* shard-iclb: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb1/igt@gem_exec_fair@basic-pace@vecs0.html> ([i915#2842]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@gem_exec_fair@basic-pace@vecs0.html>
* igt@gem_exec_fair@basic-throttle@rcs0:
* shard-iclb: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html> ([i915#2849]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html>
* igt@i915_pm_rpm@system-suspend-modeset:
* shard-tglb: INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-tglb7/igt@i915_pm_rpm@system-suspend-modeset.html> ([i915#2411] / [i915#456]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb5/igt@i915_pm_rpm@system-suspend-modeset.html> +1 similar issue
* igt@i915_selftest@live@hangcheck:
* shard-iclb: INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb6/igt@i915_selftest@live@hangcheck.html> ([i915#3965]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@i915_selftest@live@hangcheck.html>
* igt@i915_suspend@debugfs-reader:
* shard-apl: DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-apl1/igt@i915_suspend@debugfs-reader.html> ([i915#180]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl7/igt@i915_suspend@debugfs-reader.html> +1 similar issue
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
* shard-skl: INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html> ([i915#2828] / [i915#300]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html>
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2:
* shard-glk: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-glk1/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html> ([i915#79]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-glk1/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html>
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
* shard-iclb: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html> ([i915#3701]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html>
* igt@kms_hdr@bpc-switch:
* shard-skl: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-skl5/igt@kms_hdr@bpc-switch.html> ([i915#1188]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl4/igt@kms_hdr@bpc-switch.html>
* igt@kms_plane@plane-position-covered@pipe-a-planes:
* shard-tglb: INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-tglb8/igt@kms_plane@plane-position-covered@pipe-a-planes.html> -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_plane@plane-position-covered@pipe-a-planes.html>
* igt@kms_psr@psr2_cursor_plane_onoff:
* shard-iclb: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb1/igt@kms_psr@psr2_cursor_plane_onoff.html> ([fdo#109441]) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html>
* igt@perf@polling-parameterized:
* shard-iclb: FAIL<https://i> ([i915#1542]) -> [PASS][138]
On Thu, Nov 04, 2021 at 11:43:31AM -0700, Sripada, Radhakrishna wrote: > Link: [1]File-List > > > > > > From: Patchwork <patchwork@emeril.freedesktop.org> > Sent: Friday, October 15, 2021 6:48 PM > To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com> > Cc: intel-gfx@lists.freedesktop.org > Subject: ✗ Fi.CI.IGT: failure for drm/i915: Update memory bandwidth > formulae (rev9) > > > > Patch Details > > Series: drm/i915: Update memory bandwidth formulae (rev9) > URL: [2]https://patchwork.freedesktop.org/series/95138/ > State: failure > Details: [3]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/index.html > > CI Bug Log - changes from CI_DRM_10744_full -> Patchwork_21357_full > > Summary > > FAILURE > > Serious unknown changes coming with Patchwork_21357_full absolutely need > to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_21357_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in > CI. > > Possible new issues > > Here are the unknown changes that may have been introduced in > Patchwork_21357_full: > > IGT changes > > Possible regressions > > o igt@kms_bw@linear-tiling-6-displays-3840x2160p: > > o shard-tglb: NOTRUN -> [4]SKIP > > RK: This test looks flaky and has failed across multiple platforms. The > error does not indicate issue wrt bw calculations and > can be ignored. Applied to drm-intel-next. Thanks for the patch and the review. Matt > > > > Thanks, > > Radhakrishna Sripada > > Warnings > > o igt@runner@aborted: > > o shard-iclb: ([5]FAIL, [6]FAIL, [7]FAIL, [8]FAIL, [9]FAIL, [10]FAIL) > ([i915#3002] / [i915#4006]) -> ([11]FAIL, [12]FAIL, [13]FAIL, > [14]FAIL, [15]FAIL) ([i915#3002]) > > Known issues > > Here are the changes found in Patchwork_21357_full that come from known > issues: > > IGT changes > > Issues hit > > o igt@gem_create@create-massive: > > o shard-apl: NOTRUN -> [16]DMESG-WARN ([i915#3002]) > > o igt@gem_ctx_persistence@engines-hang: > > o shard-snb: NOTRUN -> [17]SKIP ([fdo#109271] / [i915#1099]) > > o igt@gem_ctx_sseu@invalid-args: > > o shard-tglb: NOTRUN -> [18]SKIP ([i915#280]) > > o igt@gem_exec_fair@basic-none-solo@rcs0: > > o shard-kbl: NOTRUN -> [19]FAIL ([i915#2842]) > > o igt@gem_exec_fair@basic-none-vip@rcs0: > > o shard-kbl: [20]PASS -> [21]FAIL ([i915#2842]) > > o igt@gem_exec_fair@basic-pace-share@rcs0: > > o shard-tglb: NOTRUN -> [22]FAIL ([i915#2842]) > > o igt@gem_exec_fair@basic-pace-solo@rcs0: > > o shard-glk: [23]PASS -> [24]FAIL ([i915#2842]) +1 similar issue > > o igt@gem_exec_params@no-bsd: > > o shard-tglb: NOTRUN -> [25]SKIP ([fdo#109283]) > > o igt@gem_pread@exhaustion: > > o shard-apl: NOTRUN -> [26]WARN ([i915#2658]) > o shard-kbl: NOTRUN -> [27]WARN ([i915#2658]) > > o igt@gem_pxp@verify-pxp-key-change-after-suspend-resume: > > o shard-tglb: NOTRUN -> [28]SKIP ([i915#4270]) > > o igt@gem_softpin@allocator-basic-reserve: > > o shard-skl: [29]PASS -> [30]DMESG-WARN ([i915#1982]) > > o igt@gem_userptr_blits@create-destroy-unsync: > > o shard-tglb: NOTRUN -> [31]SKIP ([i915#3297]) > > o igt@gem_userptr_blits@input-checking: > > o shard-skl: NOTRUN -> [32]DMESG-WARN ([i915#3002]) > > o igt@gen3_render_tiledy_blits: > > o shard-iclb: NOTRUN -> [33]SKIP ([fdo#109289]) > > o igt@gen9_exec_parse@basic-rejected: > > o shard-tglb: NOTRUN -> [34]SKIP ([i915#2856]) > > o igt@gen9_exec_parse@unaligned-access: > > o shard-iclb: NOTRUN -> [35]SKIP ([i915#2856]) > > o igt@kms_big_fb@linear-32bpp-rotate-0: > > o shard-glk: [36]PASS -> [37]DMESG-WARN ([i915#118]) > > o igt@kms_big_fb@x-tiled-16bpp-rotate-90: > > o shard-tglb: NOTRUN -> [38]SKIP ([fdo#111614]) +1 similar issue > > o igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip: > > o shard-kbl: NOTRUN -> [39]SKIP ([fdo#109271] / [i915#3777]) +1 > similar issue > o shard-apl: NOTRUN -> [40]SKIP ([fdo#109271] / [i915#3777]) +1 > similar issue > > o igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip: > > o shard-skl: NOTRUN -> [41]FAIL ([i915#3722]) > > o igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip: > > o shard-tglb: NOTRUN -> [42]SKIP ([fdo#111615]) > > o igt@kms_big_joiner@basic: > > o shard-iclb: NOTRUN -> [43]SKIP ([i915#2705]) > > o igt@kms_bw@linear-tiling-4-displays-3840x2160p: > > o shard-tglb: NOTRUN -> [44]FAIL ([i915#1385]) > > o igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc: > > o shard-iclb: NOTRUN -> [45]SKIP ([fdo#109278] / [i915#3886]) > > o igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc: > > o shard-skl: NOTRUN -> [46]SKIP ([fdo#109271] / [i915#3886]) > > o igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs: > > o shard-snb: NOTRUN -> [47]SKIP ([fdo#109271]) +218 similar issues > > o igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc: > > o shard-kbl: NOTRUN -> [48]SKIP ([fdo#109271] / [i915#3886]) +5 > similar issues > > o igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc: > > o shard-apl: NOTRUN -> [49]SKIP ([fdo#109271] / [i915#3886]) +8 > similar issues > > o igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs: > > o shard-tglb: NOTRUN -> [50]SKIP ([i915#3689] / [i915#3886]) > > o igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs: > > o shard-iclb: NOTRUN -> [51]SKIP ([fdo#109278]) +7 similar issues > > o igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs: > > o shard-tglb: NOTRUN -> [52]SKIP ([i915#3689]) +1 similar issue > > o igt@kms_chamelium@dp-edid-change-during-suspend: > > o shard-iclb: NOTRUN -> [53]SKIP ([fdo#109284] / [fdo#111827]) +3 > similar issues > > o igt@kms_chamelium@hdmi-audio-edid: > > o shard-kbl: NOTRUN -> [54]SKIP ([fdo#109271] / [fdo#111827]) +10 > similar issues > > o igt@kms_chamelium@vga-hpd: > > o shard-apl: NOTRUN -> [55]SKIP ([fdo#109271] / [fdo#111827]) +19 > similar issues > > o igt@kms_chamelium@vga-hpd-for-each-pipe: > > o shard-skl: NOTRUN -> [56]SKIP ([fdo#109271] / [fdo#111827]) +7 > similar issues > > o igt@kms_chamelium@vga-hpd-without-ddc: > > o shard-snb: NOTRUN -> [57]SKIP ([fdo#109271] / [fdo#111827]) +11 > similar issues > > o igt@kms_color_chamelium@pipe-d-ctm-max: > > o shard-tglb: NOTRUN -> [58]SKIP ([fdo#109284] / [fdo#111827]) +7 > similar issues > > o igt@kms_content_protection@atomic: > > o shard-kbl: NOTRUN -> [59]TIMEOUT ([i915#1319]) +1 similar issue > o shard-apl: NOTRUN -> [60]TIMEOUT ([i915#1319]) > > o igt@kms_content_protection@dp-mst-type-0: > > o shard-tglb: NOTRUN -> [61]SKIP ([i915#3116]) > > o igt@kms_content_protection@type1: > > o shard-tglb: NOTRUN -> [62]SKIP ([fdo#111828]) > > o igt@kms_cursor_crc@pipe-a-cursor-512x512-onscreen: > > o shard-tglb: NOTRUN -> [63]SKIP ([fdo#109279] / [i915#3359]) +2 > similar issues > > o igt@kms_cursor_crc@pipe-d-cursor-max-size-sliding: > > o shard-tglb: NOTRUN -> [64]SKIP ([i915#3359]) +2 similar issues > > o igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: > > o shard-glk: [65]PASS -> [66]FAIL ([i915#72]) > > o igt@kms_cursor_legacy@cursora-vs-flipb-atomic: > > o shard-iclb: NOTRUN -> [67]SKIP ([fdo#109274] / [fdo#109278]) > > o igt@kms_cursor_legacy@flip-vs-cursor-legacy: > > o shard-skl: [68]PASS -> [69]FAIL ([i915#2346]) > > o igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2: > > o shard-glk: [70]PASS -> [71]FAIL ([i915#79]) +1 similar issue > > o igt@kms_flip@flip-vs-expired-vblank@a-dp1: > > o shard-apl: NOTRUN -> [72]FAIL ([i915#79]) > > o igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1: > > o shard-skl: [73]PASS -> [74]FAIL ([i915#2122]) +1 similar issue > > o igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile: > > o shard-tglb: NOTRUN -> [75]SKIP ([i915#2587]) > > o igt@kms_frontbuffer_tracking@fbc-suspend: > > o shard-kbl: [76]PASS -> [77]DMESG-WARN ([i915#180]) +2 similar > issues > > o igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt: > > o shard-skl: NOTRUN -> [78]SKIP ([fdo#109271]) +66 similar issues > > o igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt: > > o shard-tglb: NOTRUN -> [79]SKIP ([fdo#111825]) +16 similar issues > > o igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render: > > o shard-iclb: NOTRUN -> [80]SKIP ([fdo#109280]) +3 similar issues > > o igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite: > > o shard-apl: NOTRUN -> [81]SKIP ([fdo#109271]) +204 similar issues > > o igt@kms_hdr@static-toggle-dpms: > > o shard-tglb: NOTRUN -> [82]SKIP ([i915#1187]) > > o igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes: > > o shard-tglb: NOTRUN -> [83]SKIP ([fdo#109289]) > > o igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes: > > o shard-apl: [84]PASS -> [85]DMESG-WARN ([i915#180]) +1 similar issue > > o igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes: > > o shard-tglb: [86]PASS -> [87]INCOMPLETE ([i915#456]) > > o igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: > > o shard-apl: NOTRUN -> [88]FAIL ([fdo#108145] / [i915#265]) +3 > similar issues > > o igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb: > > o shard-kbl: NOTRUN -> [89]FAIL ([fdo#108145] / [i915#265]) > > o igt@kms_plane_alpha_blend@pipe-c-alpha-basic: > > o shard-skl: NOTRUN -> [90]FAIL ([fdo#108145] / [i915#265]) > > o igt@kms_plane_lowres@pipe-b-tiling-y: > > o shard-tglb: NOTRUN -> [91]SKIP ([i915#3536]) > > o igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4: > > o shard-tglb: NOTRUN -> [92]SKIP ([i915#2920]) +1 similar issue > > o igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2: > > o shard-kbl: NOTRUN -> [93]SKIP ([fdo#109271] / [i915#658]) +2 > similar issues > > o igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4: > > o shard-skl: NOTRUN -> [94]SKIP ([fdo#109271] / [i915#658]) > > o igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5: > > o shard-apl: NOTRUN -> [95]SKIP ([fdo#109271] / [i915#658]) +1 > similar issue > > o igt@kms_psr@psr2_cursor_blt: > > o shard-tglb: NOTRUN -> [96]FAIL ([i915#132] / [i915#3467]) > > o igt@kms_psr@psr2_cursor_mmap_cpu: > > o shard-iclb: NOTRUN -> [97]SKIP ([fdo#109441]) > > o igt@kms_setmode@basic: > > o shard-snb: NOTRUN -> [98]FAIL ([i915#31]) > > o igt@kms_vblank@pipe-d-wait-idle: > > o shard-kbl: NOTRUN -> [99]SKIP ([fdo#109271] / [i915#533]) +1 > similar issue > o shard-apl: NOTRUN -> [100]SKIP ([fdo#109271] / [i915#533]) +1 > similar issue > > o igt@kms_writeback@writeback-check-output: > > o shard-iclb: NOTRUN -> [101]SKIP ([i915#2437]) > > o igt@kms_writeback@writeback-fb-id: > > o shard-apl: NOTRUN -> [102]SKIP ([fdo#109271] / [i915#2437]) +1 > similar issue > > o igt@nouveau_crc@ctx-flip-threshold-reset-after-capture: > > o shard-tglb: NOTRUN -> [103]SKIP ([i915#2530]) > > o igt@prime_nv_api@i915_nv_import_twice_check_flink_name: > > o shard-tglb: NOTRUN -> [104]SKIP ([fdo#109291]) +1 similar issue > > o igt@prime_nv_pcopy@test2: > > o shard-kbl: NOTRUN -> [105]SKIP ([fdo#109271]) +113 similar issues > > o igt@prime_nv_pcopy@test3_3: > > o shard-iclb: NOTRUN -> [106]SKIP ([fdo#109291]) > > o igt@sysfs_clients@fair-7: > > o shard-tglb: NOTRUN -> [107]SKIP ([i915#2994]) > > o igt@sysfs_clients@pidname: > > o shard-apl: NOTRUN -> [108]SKIP ([fdo#109271] / [i915#2994]) +3 > similar issues > > o igt@sysfs_clients@split-25: > > o shard-kbl: NOTRUN -> [109]SKIP ([fdo#109271] / [i915#2994]) > > Possible fixes > > o igt@gem_ctx_isolation@preservation-s3@bcs0: > > o shard-tglb: [110]INCOMPLETE ([i915#456]) -> [111]PASS > o shard-kbl: [112]DMESG-WARN ([i915#180]) -> [113]PASS +6 similar > issues > > o igt@gem_ctx_persistence@engines-hostile@vecs0: > > o shard-kbl: [114]FAIL ([i915#2410]) -> [115]PASS > > o igt@gem_exec_fair@basic-pace@vecs0: > > o shard-glk: [116]FAIL ([i915#2842]) -> [117]PASS > o shard-iclb: [118]FAIL ([i915#2842]) -> [119]PASS > > o igt@gem_exec_fair@basic-throttle@rcs0: > > o shard-iclb: [120]FAIL ([i915#2849]) -> [121]PASS > > o igt@i915_pm_rpm@system-suspend-modeset: > > o shard-tglb: [122]INCOMPLETE ([i915#2411] / [i915#456]) -> [123]PASS > +1 similar issue > > o igt@i915_selftest@live@hangcheck: > > o shard-iclb: [124]INCOMPLETE ([i915#3965]) -> [125]PASS > > o igt@i915_suspend@debugfs-reader: > > o shard-apl: [126]DMESG-WARN ([i915#180]) -> [127]PASS +1 similar > issue > > o igt@kms_cursor_crc@pipe-a-cursor-suspend: > > o shard-skl: [128]INCOMPLETE ([i915#2828] / [i915#300]) -> [129]PASS > > o igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2: > > o shard-glk: [130]FAIL ([i915#79]) -> [131]PASS > > o igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs: > > o shard-iclb: [132]SKIP ([i915#3701]) -> [133]PASS > > o igt@kms_hdr@bpc-switch: > > o shard-skl: [134]FAIL ([i915#1188]) -> [135]PASS > > o igt@kms_plane@plane-position-covered@pipe-a-planes: > > o shard-tglb: [136]INCOMPLETE -> [137]PASS > > o igt@kms_psr@psr2_cursor_plane_onoff: > > o shard-iclb: [138]SKIP ([fdo#109441]) -> [139]PASS > > o igt@perf@polling-parameterized: > > o shard-iclb: [140]FAIL ([i915#1542]) -> [PASS][138] > > References > > Visible links > 1. file:///tmp/cid:filelist.xml@01D7D171.2F8E17F0 > 2. https://patchwork.freedesktop.org/series/95138/ > 3. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/index.html > 4. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb5/igt@kms_bw@linear-tiling-6-displays-3840x2160p.html > 5. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb3/igt@runner@aborted.html > 6. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb4/igt@runner@aborted.html > 7. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb6/igt@runner@aborted.html > 8. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb4/igt@runner@aborted.html > 9. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb8/igt@runner@aborted.html > 10. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb5/igt@runner@aborted.html > 11. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb1/igt@runner@aborted.html > 12. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb4/igt@runner@aborted.html > 13. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb5/igt@runner@aborted.html > 14. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb5/igt@runner@aborted.html > 15. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb7/igt@runner@aborted.html > 16. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl6/igt@gem_create@create-massive.html > 17. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-snb5/igt@gem_ctx_persistence@engines-hang.html > 18. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@gem_ctx_sseu@invalid-args.html > 19. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl6/igt@gem_exec_fair@basic-none-solo@rcs0.html > 20. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-kbl1/igt@gem_exec_fair@basic-none-vip@rcs0.html > 21. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl4/igt@gem_exec_fair@basic-none-vip@rcs0.html > 22. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html > 23. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-glk1/igt@gem_exec_fair@basic-pace-solo@rcs0.html > 24. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-glk1/igt@gem_exec_fair@basic-pace-solo@rcs0.html > 25. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb3/igt@gem_exec_params@no-bsd.html > 26. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl1/igt@gem_pread@exhaustion.html > 27. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl6/igt@gem_pread@exhaustion.html > 28. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb1/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html > 29. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-skl7/igt@gem_softpin@allocator-basic-reserve.html > 30. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl8/igt@gem_softpin@allocator-basic-reserve.html > 31. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb1/igt@gem_userptr_blits@create-destroy-unsync.html > 32. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl10/igt@gem_userptr_blits@input-checking.html > 33. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@gen3_render_tiledy_blits.html > 34. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb3/igt@gen9_exec_parse@basic-rejected.html > 35. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@gen9_exec_parse@unaligned-access.html > 36. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-glk7/igt@kms_big_fb@linear-32bpp-rotate-0.html > 37. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-glk5/igt@kms_big_fb@linear-32bpp-rotate-0.html > 38. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb2/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html > 39. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html > 40. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html > 41. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl10/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html > 42. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html > 43. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@kms_big_joiner@basic.html > 44. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_bw@linear-tiling-4-displays-3840x2160p.html > 45. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html > 46. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl1/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html > 47. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-snb5/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs.html > 48. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl7/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html > 49. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl3/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html > 50. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb3/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html > 51. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs.html > 52. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb1/igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs.html > 53. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@kms_chamelium@dp-edid-change-during-suspend.html > 54. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl3/igt@kms_chamelium@hdmi-audio-edid.html > 55. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl2/igt@kms_chamelium@vga-hpd.html > 56. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl7/igt@kms_chamelium@vga-hpd-for-each-pipe.html > 57. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-snb5/igt@kms_chamelium@vga-hpd-without-ddc.html > 58. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb1/igt@kms_color_chamelium@pipe-d-ctm-max.html > 59. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl6/igt@kms_content_protection@atomic.html > 60. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl1/igt@kms_content_protection@atomic.html > 61. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_content_protection@dp-mst-type-0.html > 62. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_content_protection@type1.html > 63. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_cursor_crc@pipe-a-cursor-512x512-onscreen.html > 64. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-max-size-sliding.html > 65. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html > 66. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html > 67. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html > 68. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html > 69. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html > 70. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html > 71. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html > 72. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl2/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html > 73. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html > 74. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html > 75. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html > 76. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html > 77. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html > 78. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl7/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt.html > 79. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html > 80. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render.html > 81. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite.html > 82. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb2/igt@kms_hdr@static-toggle-dpms.html > 83. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html > 84. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html > 85. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html > 86. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-tglb3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html > 87. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html > 88. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html > 89. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl6/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html > 90. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html > 91. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb3/igt@kms_plane_lowres@pipe-b-tiling-y.html > 92. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html > 93. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html > 94. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl10/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html > 95. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl8/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html > 96. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_psr@psr2_cursor_blt.html > 97. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_cpu.html > 98. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-snb7/igt@kms_setmode@basic.html > 99. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl6/igt@kms_vblank@pipe-d-wait-idle.html > 100. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl1/igt@kms_vblank@pipe-d-wait-idle.html > 101. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@kms_writeback@writeback-check-output.html > 102. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl3/igt@kms_writeback@writeback-fb-id.html > 103. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@nouveau_crc@ctx-flip-threshold-reset-after-capture.html > 104. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb1/igt@prime_nv_api@i915_nv_import_twice_check_flink_name.html > 105. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl6/igt@prime_nv_pcopy@test2.html > 106. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@prime_nv_pcopy@test3_3.html > 107. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@sysfs_clients@fair-7.html > 108. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl8/igt@sysfs_clients@pidname.html > 109. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl6/igt@sysfs_clients@split-25.html > 110. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-tglb7/igt@gem_ctx_isolation@preservation-s3@bcs0.html > 111. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb3/igt@gem_ctx_isolation@preservation-s3@bcs0.html > 112. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html > 113. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@bcs0.html > 114. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-kbl3/igt@gem_ctx_persistence@engines-hostile@vecs0.html > 115. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-kbl7/igt@gem_ctx_persistence@engines-hostile@vecs0.html > 116. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-glk4/igt@gem_exec_fair@basic-pace@vecs0.html > 117. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-glk6/igt@gem_exec_fair@basic-pace@vecs0.html > 118. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb1/igt@gem_exec_fair@basic-pace@vecs0.html > 119. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@gem_exec_fair@basic-pace@vecs0.html > 120. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html > 121. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html > 122. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-tglb7/igt@i915_pm_rpm@system-suspend-modeset.html > 123. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb5/igt@i915_pm_rpm@system-suspend-modeset.html > 124. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb6/igt@i915_selftest@live@hangcheck.html > 125. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb8/igt@i915_selftest@live@hangcheck.html > 126. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-apl1/igt@i915_suspend@debugfs-reader.html > 127. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-apl7/igt@i915_suspend@debugfs-reader.html > 128. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html > 129. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html > 130. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-glk1/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html > 131. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-glk1/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html > 132. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html > 133. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html > 134. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-skl5/igt@kms_hdr@bpc-switch.html > 135. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-skl4/igt@kms_hdr@bpc-switch.html > 136. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-tglb8/igt@kms_plane@plane-position-covered@pipe-a-planes.html > 137. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-tglb8/igt@kms_plane@plane-position-covered@pipe-a-planes.html > 138. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10744/shard-iclb1/igt@kms_psr@psr2_cursor_plane_onoff.html > 139. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21357/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html > 140. https://i/
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 8d9d888e9316..15c006194c85 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -27,6 +27,9 @@ struct intel_qgv_info { u8 num_points; u8 num_psf_points; u8 t_bl; + u8 max_numchannels; + u8 channel_width; + u8 deinterleave; }; static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv, @@ -42,7 +45,7 @@ static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv, dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */ else dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */ - sp->dclk = dclk_ratio * dclk_reference; + sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000); val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); if (val & DG1_GEAR_TYPE) @@ -69,6 +72,7 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv, int point) { u32 val = 0, val2 = 0; + u16 dclk; int ret; ret = sandybridge_pcode_read(dev_priv, @@ -78,7 +82,8 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv, if (ret) return ret; - sp->dclk = val & 0xffff; + dclk = val & 0xffff; + sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) > 11 ? 500 : 0), 1000); sp->t_rp = (val & 0xff0000) >> 16; sp->t_rcd = (val & 0xff000000) >> 24; @@ -133,7 +138,8 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv, } static int icl_get_qgv_points(struct drm_i915_private *dev_priv, - struct intel_qgv_info *qi) + struct intel_qgv_info *qi, + bool is_y_tile) { const struct dram_info *dram_info = &dev_priv->dram_info; int i, ret; @@ -144,17 +150,41 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv, if (DISPLAY_VER(dev_priv) == 12) switch (dram_info->type) { case INTEL_DRAM_DDR4: - qi->t_bl = 4; + qi->t_bl = is_y_tile ? 8 : 4; + qi->max_numchannels = 2; + qi->channel_width = 64; + qi->deinterleave = is_y_tile ? 1 : 2; break; case INTEL_DRAM_DDR5: - qi->t_bl = 8; + qi->t_bl = is_y_tile ? 16 : 8; + qi->max_numchannels = 4; + qi->channel_width = 32; + qi->deinterleave = is_y_tile ? 1 : 2; + break; + case INTEL_DRAM_LPDDR4: + if (IS_ROCKETLAKE(dev_priv)) { + qi->t_bl = 8; + qi->max_numchannels = 4; + qi->channel_width = 32; + qi->deinterleave = 2; + break; + } + fallthrough; + case INTEL_DRAM_LPDDR5: + qi->t_bl = 16; + qi->max_numchannels = 8; + qi->channel_width = 16; + qi->deinterleave = is_y_tile ? 2 : 4; break; default: qi->t_bl = 16; + qi->max_numchannels = 1; break; } - else if (DISPLAY_VER(dev_priv) == 11) + else if (DISPLAY_VER(dev_priv) == 11) { qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8; + qi->max_numchannels = 1; + } if (drm_WARN_ON(&dev_priv->drm, qi->num_points > ARRAY_SIZE(qi->points))) @@ -193,12 +223,6 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv, return 0; } -static int icl_calc_bw(int dclk, int num, int den) -{ - /* multiples of 16.666MHz (100/6) */ - return DIV_ROUND_CLOSEST(num * dclk * 100, den * 6); -} - static int adl_calc_psf_bw(int clk) { /* @@ -240,7 +264,7 @@ static const struct intel_sa_info tgl_sa_info = { }; static const struct intel_sa_info rkl_sa_info = { - .deburst = 16, + .deburst = 8, .deprogbwlimit = 20, /* GB/s */ .displayrtids = 128, .derating = 10, @@ -265,35 +289,130 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel struct intel_qgv_info qi = {}; bool is_y_tile = true; /* assume y tile may be used */ int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels); - int deinterleave; - int ipqdepth, ipqdepthpch; + int ipqdepth, ipqdepthpch = 16; int dclk_max; int maxdebw; + int num_groups = ARRAY_SIZE(dev_priv->max_bw); int i, ret; - ret = icl_get_qgv_points(dev_priv, &qi); + ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile); if (ret) { drm_dbg_kms(&dev_priv->drm, "Failed to get memory subsystem information, ignoring bandwidth limits"); return ret; } - deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2); dclk_max = icl_sagv_max_dclk(&qi); + maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10); + ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels); + qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2); + + for (i = 0; i < num_groups; i++) { + struct intel_bw_info *bi = &dev_priv->max_bw[i]; + int clpchgroup; + int j; + + clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i; + bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1; + + bi->num_qgv_points = qi.num_points; + bi->num_psf_gv_points = qi.num_psf_points; + + for (j = 0; j < qi.num_points; j++) { + const struct intel_qgv_point *sp = &qi.points[j]; + int ct, bw; + + /* + * Max row cycle time + * + * FIXME what is the logic behind the + * assumed burst length? + */ + ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd + + (clpchgroup - 1) * qi.t_bl + sp->t_rdpre); + bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct); - ipqdepthpch = 16; + bi->deratedbw[j] = min(maxdebw, + bw * (100 - sa->derating) / 100); + + drm_dbg_kms(&dev_priv->drm, + "BW%d / QGV %d: num_planes=%d deratedbw=%u\n", + i, j, bi->num_planes, bi->deratedbw[j]); + } + } + /* + * In case if SAGV is disabled in BIOS, we always get 1 + * SAGV point, but we can't send PCode commands to restrict it + * as it will fail and pointless anyway. + */ + if (qi.num_points == 1) + dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; + else + dev_priv->sagv_status = I915_SAGV_ENABLED; + + return 0; +} + +static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa) +{ + struct intel_qgv_info qi = {}; + const struct dram_info *dram_info = &dev_priv->dram_info; + bool is_y_tile = true; /* assume y tile may be used */ + int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels); + int ipqdepth, ipqdepthpch = 16; + int dclk_max; + int maxdebw, peakbw; + int clperchgroup; + int num_groups = ARRAY_SIZE(dev_priv->max_bw); + int i, ret; + + ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile); + if (ret) { + drm_dbg_kms(&dev_priv->drm, + "Failed to get memory subsystem information, ignoring bandwidth limits"); + return ret; + } + + if (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == INTEL_DRAM_LPDDR5) + num_channels *= 2; + + qi.deinterleave = qi.deinterleave ? : DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2); + + if (num_channels < qi.max_numchannels && DISPLAY_VER(dev_priv) >= 12) + qi.deinterleave = max(DIV_ROUND_UP(qi.deinterleave, 2), 1); + + if (DISPLAY_VER(dev_priv) > 11 && num_channels > qi.max_numchannels) + drm_warn(&dev_priv->drm, "Number of channels exceeds max number of channels."); + if (qi.max_numchannels != 0) + num_channels = min_t(u8, num_channels, qi.max_numchannels); + + dclk_max = icl_sagv_max_dclk(&qi); + + peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max; + maxdebw = min(sa->deprogbwlimit * 1000, peakbw * 6 / 10); /* 60% */ - maxdebw = min(sa->deprogbwlimit * 1000, - icl_calc_bw(dclk_max, 16, 1) * 6 / 10); /* 60% */ ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels); + /* + * clperchgroup = 4kpagespermempage * clperchperblock, + * clperchperblock = 8 / num_channels * interleave + */ + clperchgroup = 4 * DIV_ROUND_UP(8, num_channels) * qi.deinterleave; - for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) { + for (i = 0; i < num_groups; i++) { struct intel_bw_info *bi = &dev_priv->max_bw[i]; + struct intel_bw_info *bi_next; int clpchgroup; int j; - clpchgroup = (sa->deburst * deinterleave / num_channels) << i; - bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1; + if (i < num_groups - 1) + bi_next = &dev_priv->max_bw[i + 1]; + + clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i; + + if (i < num_groups - 1 && clpchgroup < clperchgroup) + bi_next->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1; + else + bi_next->num_planes = 0; bi->num_qgv_points = qi.num_points; bi->num_psf_gv_points = qi.num_psf_points; @@ -310,7 +429,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel */ ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd + (clpchgroup - 1) * qi.t_bl + sp->t_rdpre); - bw = icl_calc_bw(sp->dclk, clpchgroup * 32 * num_channels, ct); + bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct); bi->deratedbw[j] = min(maxdebw, bw * (100 - sa->derating) / 100); @@ -329,9 +448,6 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel "BW%d / PSF GV %d: num_planes=%d bw=%u\n", i, j, bi->num_planes, bi->psf_bw[j]); } - - if (bi->num_planes == 1) - break; } /* @@ -395,6 +511,34 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv, return 0; } +static unsigned int tgl_max_bw(struct drm_i915_private *dev_priv, + int num_planes, int qgv_point) +{ + int i; + + /* + * Let's return max bw for 0 planes + */ + num_planes = max(1, num_planes); + + for (i = ARRAY_SIZE(dev_priv->max_bw) - 1; i >= 0; i--) { + const struct intel_bw_info *bi = + &dev_priv->max_bw[i]; + + /* + * Pcode will not expose all QGV points when + * SAGV is forced to off/min/med/max. + */ + if (qgv_point >= bi->num_qgv_points) + return UINT_MAX; + + if (num_planes <= bi->num_planes) + return bi->deratedbw[qgv_point]; + } + + return dev_priv->max_bw[0].deratedbw[qgv_point]; +} + static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv, int psf_gv_point) { @@ -412,13 +556,13 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv) if (IS_DG2(dev_priv)) dg2_get_bw_info(dev_priv); else if (IS_ALDERLAKE_P(dev_priv)) - icl_get_bw_info(dev_priv, &adlp_sa_info); + tgl_get_bw_info(dev_priv, &adlp_sa_info); else if (IS_ALDERLAKE_S(dev_priv)) - icl_get_bw_info(dev_priv, &adls_sa_info); + tgl_get_bw_info(dev_priv, &adls_sa_info); else if (IS_ROCKETLAKE(dev_priv)) - icl_get_bw_info(dev_priv, &rkl_sa_info); + tgl_get_bw_info(dev_priv, &rkl_sa_info); else if (DISPLAY_VER(dev_priv) == 12) - icl_get_bw_info(dev_priv, &tgl_sa_info); + tgl_get_bw_info(dev_priv, &tgl_sa_info); else if (DISPLAY_VER(dev_priv) == 11) icl_get_bw_info(dev_priv, &icl_sa_info); } @@ -746,7 +890,10 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) for (i = 0; i < num_qgv_points; i++) { unsigned int max_data_rate; - max_data_rate = icl_max_bw(dev_priv, num_active_planes, i); + if (DISPLAY_VER(dev_priv) > 11) + max_data_rate = tgl_max_bw(dev_priv, num_active_planes, i); + else + max_data_rate = icl_max_bw(dev_priv, num_active_planes, i); /* * We need to know which qgv point gives us * maximum bandwidth in order to disable SAGV
The formulae has been updated to include more variables. Make sure the code carries the same. Bspec: 64631, 54023 v2: Make GEN11 follow the default route and fix calculation of maxdebw(RK) v3: Fix div by zero on default case Correct indent for fallthrough(Jani) v4: Fix div by zero on gen11. v5: Fix 0 max_numchannels case v6: - Split gen11/gen12 algorithms - Fix RKL deburst value - Fix difference b/ween ICL and TGL algorithms - Protect deinterleave from being 0 - Warn when numchannels exceeds max_numchannels - Fix scaling of clk_max from different units - s/deinterleave/channelwidth/ in calculating peakbw - Fix off by one for num_planes TGL+ - Fix SAGV check v7: Fix div by zero error on gen11 v8: Even though the algorithm for gen11 says that we need to return derated bw for a qgv point whose planes are less than no of active planes, we return 0 for deratedbw when only one plane is allowed. We modify the algorithm to accommodate the case where no of active planes are same as the min no of planes supported by a qgv point. v9: Fix dclk scaling for dg1 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Suggested-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> --- drivers/gpu/drm/i915/display/intel_bw.c | 211 ++++++++++++++++++++---- 1 file changed, 179 insertions(+), 32 deletions(-)