Message ID | 20211105150146.834052-1-thomas.hellstrom@linux.intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v3,1/2] drm/i915/selftests: Use clear_and_wake_up_bit() for the per-engine reset bitlocks | expand |
On 11/5/21 17:55, Patchwork wrote: > Project List - Patchwork *Patch Details* > *Series:* series starting with [v3,1/2] drm/i915/selftests: Use > clear_and_wake_up_bit() for the per-engine reset bitlocks > *URL:* https://patchwork.freedesktop.org/series/96615/ > *State:* failure > *Details:* > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21526/index.html > > > CI Bug Log - changes from CI_DRM_10846_full -> Patchwork_21526_full > > > Summary > > *FAILURE* > > Serious unknown changes coming with Patchwork_21526_full absolutely > need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_21526_full, please notify your bug team to > allow them > to document this new failure mode, which will reduce false positives > in CI. > > > Participating hosts (11 -> 11) > > No changes in participating hosts > > > Possible new issues > > Here are the unknown changes that may have been introduced in > Patchwork_21526_full: > > > IGT changes > > > Possible regressions > > * igt@kms_flip@basic-flip-vs-dpms@c-edp1: > o shard-tglb: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10846/shard-tglb3/igt@kms_flip@basic-flip-vs-dpms@c-edp1.html> > -> INCOMPLETE > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21526/shard-tglb6/igt@kms_flip@basic-flip-vs-dpms@c-edp1.html> > Lakshmi, This failure is unrelated. Thanks, Thomas
Below issue filed and re-reported.
https://gitlab.freedesktop.org/drm/intel/-/issues/4457
igt@kms_flip@basic-flip-vs-dpms@c-edp1 - incomplete - No warnings/errors
Lakshmi.
From: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Sent: Monday, November 8, 2021 12:10 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Subject: Re: ✗ Fi.CI.IGT: failure for series starting with [v3,1/2] drm/i915/selftests: Use clear_and_wake_up_bit() for the per-engine reset bitlocks
On 11/5/21 17:55, Patchwork wrote:
Patch Details
Series:
series starting with [v3,1/2] drm/i915/selftests: Use clear_and_wake_up_bit() for the per-engine reset bitlocks
URL:
https://patchwork.freedesktop.org/series/96615/
State:
failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21526/index.html
CI Bug Log - changes from CI_DRM_10846_full -> Patchwork_21526_full
Summary
FAILURE
Serious unknown changes coming with Patchwork_21526_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21526_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 11)
No changes in participating hosts
Possible new issues
Here are the unknown changes that may have been introduced in Patchwork_21526_full:
IGT changes
Possible regressions
* igt@kms_flip@basic-flip-vs-dpms@c-edp1:
* shard-tglb: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10846/shard-tglb3/igt@kms_flip@basic-flip-vs-dpms@c-edp1.html> -> INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21526/shard-tglb6/igt@kms_flip@basic-flip-vs-dpms@c-edp1.html>
Lakshmi,
This failure is unrelated.
Thanks,
Thomas
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 7e2d99dd012d..e5ad4d5a91c0 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -471,7 +471,8 @@ static int igt_reset_nop_engine(void *arg) count = 0; st_engine_heartbeat_disable(engine); - set_bit(I915_RESET_ENGINE + id, >->reset.flags); + GEM_BUG_ON(test_and_set_bit(I915_RESET_ENGINE + id, + >->reset.flags)); do { int i; @@ -528,7 +529,7 @@ static int igt_reset_nop_engine(void *arg) break; } } while (time_before(jiffies, end_time)); - clear_bit(I915_RESET_ENGINE + id, >->reset.flags); + clear_and_wake_up_bit(I915_RESET_ENGINE + id, >->reset.flags); st_engine_heartbeat_enable(engine); pr_info("%s(%s): %d resets\n", __func__, engine->name, count); @@ -582,7 +583,8 @@ static int igt_reset_fail_engine(void *arg) } st_engine_heartbeat_disable(engine); - set_bit(I915_RESET_ENGINE + id, >->reset.flags); + GEM_BUG_ON(test_and_set_bit(I915_RESET_ENGINE + id, + >->reset.flags)); force_reset_timeout(engine); err = intel_engine_reset(engine, NULL); @@ -679,7 +681,7 @@ static int igt_reset_fail_engine(void *arg) out: pr_info("%s(%s): %d resets\n", __func__, engine->name, count); skip: - clear_bit(I915_RESET_ENGINE + id, >->reset.flags); + clear_and_wake_up_bit(I915_RESET_ENGINE + id, >->reset.flags); st_engine_heartbeat_enable(engine); intel_context_put(ce); @@ -734,7 +736,8 @@ static int __igt_reset_engine(struct intel_gt *gt, bool active) reset_engine_count = i915_reset_engine_count(global, engine); st_engine_heartbeat_disable(engine); - set_bit(I915_RESET_ENGINE + id, >->reset.flags); + GEM_BUG_ON(test_and_set_bit(I915_RESET_ENGINE + id, + >->reset.flags)); count = 0; do { struct i915_request *rq = NULL; @@ -824,7 +827,7 @@ static int __igt_reset_engine(struct intel_gt *gt, bool active) if (err) break; } while (time_before(jiffies, end_time)); - clear_bit(I915_RESET_ENGINE + id, >->reset.flags); + clear_and_wake_up_bit(I915_RESET_ENGINE + id, >->reset.flags); st_engine_heartbeat_enable(engine); pr_info("%s: Completed %lu %s resets\n", engine->name, count, active ? "active" : "idle"); @@ -1042,7 +1045,8 @@ static int __igt_reset_engines(struct intel_gt *gt, yield(); /* start all threads before we begin */ st_engine_heartbeat_disable_no_pm(engine); - set_bit(I915_RESET_ENGINE + id, >->reset.flags); + GEM_BUG_ON(test_and_set_bit(I915_RESET_ENGINE + id, + >->reset.flags)); do { struct i915_request *rq = NULL; struct intel_selftest_saved_policy saved; @@ -1165,7 +1169,7 @@ static int __igt_reset_engines(struct intel_gt *gt, if (err) break; } while (time_before(jiffies, end_time)); - clear_bit(I915_RESET_ENGINE + id, >->reset.flags); + clear_and_wake_up_bit(I915_RESET_ENGINE + id, >->reset.flags); st_engine_heartbeat_enable_no_pm(engine); pr_info("i915_reset_engine(%s:%s): %lu resets\n", diff --git a/drivers/gpu/drm/i915/selftests/igt_reset.c b/drivers/gpu/drm/i915/selftests/igt_reset.c index 9f8590b868a9..a2838c65f8a5 100644 --- a/drivers/gpu/drm/i915/selftests/igt_reset.c +++ b/drivers/gpu/drm/i915/selftests/igt_reset.c @@ -36,7 +36,7 @@ void igt_global_reset_unlock(struct intel_gt *gt) enum intel_engine_id id; for_each_engine(engine, gt, id) - clear_bit(I915_RESET_ENGINE + id, >->reset.flags); + clear_and_wake_up_bit(I915_RESET_ENGINE + id, >->reset.flags); clear_bit(I915_RESET_BACKOFF, >->reset.flags); wake_up_all(>->reset.queue);