diff mbox series

[v8,3/8] dt-bindings: PCI: Add bindings for Brcmstb EP voltage regulators

Message ID 20211110221456.11977-4-jim2101024@gmail.com (mailing list archive)
State Superseded
Delegated to: Lorenzo Pieralisi
Headers show
Series PCI: brcmstb: have portdrv turn on sub-device power | expand

Commit Message

Jim Quinlan Nov. 10, 2021, 10:14 p.m. UTC
Similar to the regulator bindings found in "rockchip-pcie-host.txt", this
allows optional regulators to be attached and controlled by the PCIe RC
driver.  That being said, this driver searches in the DT subnode (the EP
node, eg pci-ep@0,0) for the regulator property.

The use of a regulator property in the pcie EP subnode such as
"vpcie12v-supply" depends on a pending pullreq to the pci-bus.yaml
file at

https://github.com/devicetree-org/dt-schema/pull/63

Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
---
 .../bindings/pci/brcm,stb-pcie.yaml           | 23 +++++++++++++++++++
 1 file changed, 23 insertions(+)

Comments

Bjorn Helgaas Nov. 11, 2021, 10:17 p.m. UTC | #1
On Wed, Nov 10, 2021 at 05:14:43PM -0500, Jim Quinlan wrote:
> Similar to the regulator bindings found in "rockchip-pcie-host.txt", this
> allows optional regulators to be attached and controlled by the PCIe RC
> driver.  That being said, this driver searches in the DT subnode (the EP
> node, eg pci-ep@0,0) for the regulator property.
> 
> The use of a regulator property in the pcie EP subnode such as
> "vpcie12v-supply" depends on a pending pullreq to the pci-bus.yaml
> file at
> 
> https://github.com/devicetree-org/dt-schema/pull/63

Can you use a lore URL here?  github.com is sort of outside the Linux
ecosystem and this link is more likely to remain useful if it's to
something in kernel.org.

The subject says what this patch does, but the commit log doesn't.
It's OK to repeat the subject in the commit log if that's what makes
the most sense.
Jim Quinlan Nov. 12, 2021, 6:25 p.m. UTC | #2
On Thu, Nov 11, 2021 at 5:17 PM Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> On Wed, Nov 10, 2021 at 05:14:43PM -0500, Jim Quinlan wrote:
> > Similar to the regulator bindings found in "rockchip-pcie-host.txt", this
> > allows optional regulators to be attached and controlled by the PCIe RC
> > driver.  That being said, this driver searches in the DT subnode (the EP
> > node, eg pci-ep@0,0) for the regulator property.
> >
> > The use of a regulator property in the pcie EP subnode such as
> > "vpcie12v-supply" depends on a pending pullreq to the pci-bus.yaml
> > file at
> >
> > https://github.com/devicetree-org/dt-schema/pull/63
>
> Can you use a lore URL here?  github.com is sort of outside the Linux
> ecosystem and this link is more likely to remain useful if it's to
> something in kernel.org.
Hi Bjorn,
I'm afraid I don't know how or if  this github repo transfers
information to Linux.  RobH, what should I be doing here?
>
> The subject says what this patch does, but the commit log doesn't.
> It's OK to repeat the subject in the commit log if that's what makes
> the most sense.
Got it.
Thanks,
Jim Quinlan
Broadcom STB
Bjorn Helgaas Nov. 12, 2021, 8:20 p.m. UTC | #3
On Fri, Nov 12, 2021 at 01:25:11PM -0500, Jim Quinlan wrote:
> On Thu, Nov 11, 2021 at 5:17 PM Bjorn Helgaas <helgaas@kernel.org> wrote:
> > On Wed, Nov 10, 2021 at 05:14:43PM -0500, Jim Quinlan wrote:
> > > Similar to the regulator bindings found in "rockchip-pcie-host.txt", this
> > > allows optional regulators to be attached and controlled by the PCIe RC
> > > driver.  That being said, this driver searches in the DT subnode (the EP
> > > node, eg pci-ep@0,0) for the regulator property.
> > >
> > > The use of a regulator property in the pcie EP subnode such as
> > > "vpcie12v-supply" depends on a pending pullreq to the pci-bus.yaml
> > > file at
> > >
> > > https://github.com/devicetree-org/dt-schema/pull/63
> >
> > Can you use a lore URL here?  github.com is sort of outside the Linux
> > ecosystem and this link is more likely to remain useful if it's to
> > something in kernel.org.
> Hi Bjorn,
> I'm afraid I don't know how or if  this github repo transfers
> information to Linux.  RobH, what should I be doing here?

Does this change get posted to any mailing lists where people can
review it?  Or would people have to watch the github devicetree-org
repo if they wanted to do that?  I was assuming this pci-bus.yaml
change was something that would eventually end up in the Linux kernel
source tree, but dt-scheme doesn't seem to be based on Linus' tree, so
I don't know if there's a connection.

Bjorn
Rob Herring (Arm) Nov. 12, 2021, 9:46 p.m. UTC | #4
On Fri, Nov 12, 2021 at 2:20 PM Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> On Fri, Nov 12, 2021 at 01:25:11PM -0500, Jim Quinlan wrote:
> > On Thu, Nov 11, 2021 at 5:17 PM Bjorn Helgaas <helgaas@kernel.org> wrote:
> > > On Wed, Nov 10, 2021 at 05:14:43PM -0500, Jim Quinlan wrote:
> > > > Similar to the regulator bindings found in "rockchip-pcie-host.txt", this
> > > > allows optional regulators to be attached and controlled by the PCIe RC
> > > > driver.  That being said, this driver searches in the DT subnode (the EP
> > > > node, eg pci-ep@0,0) for the regulator property.
> > > >
> > > > The use of a regulator property in the pcie EP subnode such as
> > > > "vpcie12v-supply" depends on a pending pullreq to the pci-bus.yaml
> > > > file at
> > > >
> > > > https://github.com/devicetree-org/dt-schema/pull/63
> > >
> > > Can you use a lore URL here?  github.com is sort of outside the Linux
> > > ecosystem and this link is more likely to remain useful if it's to
> > > something in kernel.org.
> > Hi Bjorn,
> > I'm afraid I don't know how or if  this github repo transfers
> > information to Linux.  RobH, what should I be doing here?
>
> Does this change get posted to any mailing lists where people can
> review it?

devicetree-spec is where I direct folks to. It's not in lore, but we
could add it I guess. But I take PRs too. There's so few other
contributions I'm looking to make it as painless as possible for
contributors. I'd be happy for more reviewers other than me, but I
don't think where changes are posted is the problem there. :( Someone
should review all the crap Python code I write too.

Generally the flow is I redirect things submitted to the kernel to
dtschema instead. So that review happens first at least.

> Or would people have to watch the github devicetree-org
> repo if they wanted to do that?  I was assuming this pci-bus.yaml
> change was something that would eventually end up in the Linux kernel
> source tree, but dt-scheme doesn't seem to be based on Linus' tree, so
> I don't know if there's a connection.

It's more the other way around. The 'rule' is common bindings go in
dtschema and device specific bindings in the kernel tree. Reality is
some common bindings are in the kernel tree primarily because I want
everything in dtschema dual licensed and relicensing is a pain. That's
why we have pci.txt and pci-bus.yaml still.

Rob
Pali Rohár Nov. 13, 2021, 11:38 a.m. UTC | #5
On Wednesday 10 November 2021 17:14:43 Jim Quinlan wrote:
> Similar to the regulator bindings found in "rockchip-pcie-host.txt", this
> allows optional regulators to be attached and controlled by the PCIe RC
> driver.  That being said, this driver searches in the DT subnode (the EP
> node, eg pci-ep@0,0) for the regulator property.
> 
> The use of a regulator property in the pcie EP subnode such as
> "vpcie12v-supply" depends on a pending pullreq to the pci-bus.yaml
> file at
> 
> https://github.com/devicetree-org/dt-schema/pull/63
> 
> Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> ---
>  .../bindings/pci/brcm,stb-pcie.yaml           | 23 +++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> index 508e5dce1282..ef2427320b7d 100644
> --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> @@ -158,5 +158,28 @@ examples:
>                                   <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
>                      brcm,enable-ssc;
>                      brcm,scb-sizes =  <0x0000000080000000 0x0000000080000000>;
> +
> +                    /* PCIe bridge */
> +                    pci@0,0 {

Hello! I think that above comment should be "PCIe Root Port" (and not
PCIe bridge) as this node really describes Root Port device in PCIe Root
Complex (correct me if I deduced it wrongly). lspci (-vv) show type of
device on the line "Capabilities: [..] Express".

> +                            #address-cells = <3>;
> +                            #size-cells = <2>;
> +                            reg = <0x0 0x0 0x0 0x0 0x0>;
> +                            compatible = "pciclass,0604";
> +                            device_type = "pci";
> +                            vpcie3v3-supply = <&vreg7>;
> +                            ranges;
> +
> +                            /* PCIe endpoint */
> +                            pci-ep@0,0 {
> +                                    assigned-addresses =
> +                                        <0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>;
> +                                    reg = <0x0 0x0 0x0 0x0 0x0>;
> +                                    compatible = "pci14e4,1688";
> +                                    #address-cells = <3>;
> +                                    #size-cells = <2>;
> +
> +                                    ranges;
> +                            };
> +                    };
>              };
>      };
> -- 
> 2.17.1
>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
index 508e5dce1282..ef2427320b7d 100644
--- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
@@ -158,5 +158,28 @@  examples:
                                  <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
                     brcm,enable-ssc;
                     brcm,scb-sizes =  <0x0000000080000000 0x0000000080000000>;
+
+                    /* PCIe bridge */
+                    pci@0,0 {
+                            #address-cells = <3>;
+                            #size-cells = <2>;
+                            reg = <0x0 0x0 0x0 0x0 0x0>;
+                            compatible = "pciclass,0604";
+                            device_type = "pci";
+                            vpcie3v3-supply = <&vreg7>;
+                            ranges;
+
+                            /* PCIe endpoint */
+                            pci-ep@0,0 {
+                                    assigned-addresses =
+                                        <0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>;
+                                    reg = <0x0 0x0 0x0 0x0 0x0>;
+                                    compatible = "pci14e4,1688";
+                                    #address-cells = <3>;
+                                    #size-cells = <2>;
+
+                                    ranges;
+                            };
+                    };
             };
     };