| Message ID | 1635896673-5841-1-git-send-email-quic_khsieh@quicinc.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [v3] arm64: dts: qcom: sc7280: Add Display Port node | expand |
On 2021-11-02 16:44, Kuogee Hsieh wrote: > From: Kuogee Hsieh <khsieh@codeaurora.org> > > Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> > --- Anyone has comments on this patch? > > Changes in v2: > -- move fixes of dp_phy reg property to other patch > > Changes in v3: > -- delete "qcom,sc7180-dp" from msm_dp node > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 89 > +++++++++++++++++++++++++++++++++++- > 1 file changed, 87 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi > b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index fb2f1506..4414abc 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -2709,8 +2709,8 @@ > <&gcc GCC_DISP_GPLL0_CLK_SRC>, > <&dsi_phy 0>, > <&dsi_phy 1>, > - <0>, > - <0>, > + <&dp_phy 0>, > + <&dp_phy 1>, > <&edp_phy 0>, > <&edp_phy 1>; > clock-names = "bi_tcxo", > @@ -2807,6 +2807,13 @@ > remote-endpoint = <&edp_in>; > }; > }; > + > + port@2 { > + reg = <2>; > + dpu_intf0_out: > endpoint { > + > remote-endpoint = <&dp_in>; > + }; > + }; > }; > > mdp_opp_table: opp-table { > @@ -3018,6 +3025,78 @@ > > status = "disabled"; > }; > + > + msm_dp: displayport-controller@ae90000 { > + status = "disabled"; > + compatible = "qcom,sc7280-dp"; > + > + reg = <0 0x0ae90000 0 0x1400>; > + > + interrupt-parent = <&mdss>; > + interrupts = <12>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, > + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, > + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; > + clock-names = "core_iface", > + "core_aux", > + "ctrl_link", > + "ctrl_link_iface", > + "stream_pixel"; > + #clock-cells = <1>; > + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; > + assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; > + phys = <&dp_phy>; > + phy-names = "dp"; > + > + operating-points-v2 = <&dp_opp_table>; > + power-domains = <&rpmhpd SC7280_CX>; > + > + #sound-dai-cells = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + port@0 { > + reg = <0>; > + dp_in: endpoint { > + remote-endpoint = <&dpu_intf0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dp_out: endpoint { }; > + }; > + }; > + > + dp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-160000000 { > + opp-hz = /bits/ 64 <160000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-540000000 { > + opp-hz = /bits/ 64 <540000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-810000000 { > + opp-hz = /bits/ 64 <810000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > }; > > pdc: interrupt-controller@b220000 { > @@ -3120,6 +3199,12 @@ > bias-pull-up; > }; > > + dp_hot_plug_det: dp-hot-plug-det { > + pins = "gpio47"; > + function = "dp_hot"; > + bias-disable; > + }; > + > qspi_clk: qspi-clk { > pins = "gpio14"; > function = "qspi_clk";
Quoting Kuogee Hsieh (2021-11-02 16:44:33) > From: Kuogee Hsieh <khsieh@codeaurora.org> > > Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> > --- What tree is this based on? I don't see edp_phy upstream for sc7280 Otherwise, looks good to me. Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Quoting Kuogee Hsieh (2021-11-16 08:43:38) > > On 11/15/2021 3:39 PM, Stephen Boyd wrote: > > Quoting Kuogee Hsieh (2021-11-02 16:44:33) > > From: Kuogee Hsieh <khsieh@codeaurora.org> > > Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> > --- > > What tree is this based on? I don't see edp_phy upstream for sc7280 > > this patch is depend on --> [PATCH v2 4/4] arm64: dts: qcom: sc7280: add edp > display dt nodes > > it had completed reviewed. > > https://mail.codeaurora.org/?_task=mail&_caps= > pdf%3D1%2Cflash%3D0%2Ctiff%3D0%2Cwebp%3D1&_uid=1789&_mbox=INBOX&_action=show > That email link doesn't work for anyone besides you.
On Tue 16 Nov 10:43 CST 2021, Kuogee Hsieh wrote: > > On 11/15/2021 3:39 PM, Stephen Boyd wrote: > > Quoting Kuogee Hsieh (2021-11-02 16:44:33) > > > From: Kuogee Hsieh<khsieh@codeaurora.org> > > > > > > Signed-off-by: Kuogee Hsieh<quic_khsieh@quicinc.com> > > > --- > > What tree is this based on? I don't see edp_phy upstream for sc7280 > > this patch is depend on --> [PATCH v2 4/4] arm64: dts: qcom: sc7280: add > edp display dt nodes > But there's a v3 of 3 patches in the patchworks queue, unfortunately I don't have this in my inbox. Not sure why, but looking at lore.kernel.org, you didn't use get_maintainers... Also why are the patches Reported-by: kernel test robot <lkp@intel.com>? Did lkp tell you that you where missing edp support? ;) Could you please resubmit the 4 patches together? Regards, Bjorn > it had completed reviewed. > > https://mail.codeaurora.org/?_task=mail&_caps=pdf%3D1%2Cflash%3D0%2Ctiff%3D0%2Cwebp%3D1&_uid=1789&_mbox=INBOX&_action=show > > > > > > Otherwise, looks good to me. > > > > Reviewed-by: Stephen Boyd<swboyd@chromium.org>
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index fb2f1506..4414abc 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2709,8 +2709,8 @@ <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&dsi_phy 0>, <&dsi_phy 1>, - <0>, - <0>, + <&dp_phy 0>, + <&dp_phy 1>, <&edp_phy 0>, <&edp_phy 1>; clock-names = "bi_tcxo", @@ -2807,6 +2807,13 @@ remote-endpoint = <&edp_in>; }; }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&dp_in>; + }; + }; }; mdp_opp_table: opp-table { @@ -3018,6 +3025,78 @@ status = "disabled"; }; + + msm_dp: displayport-controller@ae90000 { + status = "disabled"; + compatible = "qcom,sc7280-dp"; + + reg = <0 0x0ae90000 0 0x1400>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + #clock-cells = <1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; + phys = <&dp_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SC7280_CX>; + + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; }; pdc: interrupt-controller@b220000 { @@ -3120,6 +3199,12 @@ bias-pull-up; }; + dp_hot_plug_det: dp-hot-plug-det { + pins = "gpio47"; + function = "dp_hot"; + bias-disable; + }; + qspi_clk: qspi-clk { pins = "gpio14"; function = "qspi_clk";