| Message ID | 20211122211420.31584-1-stanislav.lisovskiy@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/dg2: Tile 4 plane format support | expand |
Hi Stanislav, Are there IGT tests for this modifier? On Mon, Nov 22, 2021 at 4:14 PM Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> wrote: > > TileF(Tile4 in bspec) format is 4K tile organized into > 64B subtiles with same basic shape as for legacy TileY > which will be supported by Display13. > > v2: - Fixed wrong case condition(Jani Nikula) > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak) > > v3: - s/I915_TILING_F/TILING_4/g > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g > - Removed unneeded fencing code > > v4: - Rebased, fixed merge conflict with new table-oriented > format modifier checking(Stan) > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan) > > v5: - Still had to remove some Tile F mentionings > - Moved has_4tile from adlp to DG2(Ramalingam C) > - Check specifically for DG2, but not the Display13(Imre) > > v6: - Moved Tile4 assocating struct for modifier/display to > the beginning(Imre Deak) > - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier > checks(Imre Deak) > - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12 > (Imre Deak) > > v7: - Fixed display_ver to { 13, 13 }(Imre Deak) > - Removed redundant newline(Imre Deak) > > Reviewed-by: Imre Deak <imre.deak@intel.com> > Cc: Imre Deak <imre.deak@intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 1 + > drivers/gpu/drm/i915/display/intel_fb.c | 9 +++++++++ > drivers/gpu/drm/i915/display/intel_fbc.c | 1 + > .../drm/i915/display/intel_plane_initial.c | 1 + > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++-------- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/i915_pci.c | 1 + > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_device_info.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 1 + > include/uapi/drm/drm_fourcc.h | 8 ++++++++ > 11 files changed, 37 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index f3c9208a30b1..7429965d3682 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int > case I915_FORMAT_MOD_X_TILED: > case I915_FORMAT_MOD_Y_TILED: > case I915_FORMAT_MOD_Yf_TILED: > + case I915_FORMAT_MOD_4_TILED: > break; > default: > drm_dbg_kms(&i915->drm, > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c > index c4a743d0913f..b7f1ef62072c 100644 > --- a/drivers/gpu/drm/i915/display/intel_fb.c > +++ b/drivers/gpu/drm/i915/display/intel_fb.c > @@ -139,6 +139,9 @@ struct intel_modifier_desc { > > static const struct intel_modifier_desc intel_modifiers[] = { > { > + .modifier = I915_FORMAT_MOD_4_TILED, > + .display_ver = { 13, 13 }, I see that every other modifier has the plane_cap field set. Why is it okay for it to be zero here? > + }, { > .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, > .display_ver = { 12, 13 }, > .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC, > @@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) > return 128; > else > return 512; > + case I915_FORMAT_MOD_4_TILED: > + /* > + * Each 4K tile consists of 64B(8*8) subtiles, with > + * same shape as Y Tile(i.e 4*16B OWords) > + */ > + return 128; > case I915_FORMAT_MOD_Y_TILED_CCS: > if (intel_fb_is_ccs_aux_plane(fb, color_plane)) > return 128; > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > index d0c34bc3af6c..0ceabe40d8c9 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -898,6 +898,7 @@ static bool tiling_is_valid(struct drm_i915_private *i915, > case I915_FORMAT_MOD_Y_TILED: > case I915_FORMAT_MOD_Yf_TILED: > return DISPLAY_VER(i915) >= 9; > + case I915_FORMAT_MOD_4_TILED: The tile Y cases above check the display version. Should we do the same here? > case I915_FORMAT_MOD_X_TILED: > return true; > default: > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c > index dcd698a02da2..d80855ee9b96 100644 > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc, > case DRM_FORMAT_MOD_LINEAR: > case I915_FORMAT_MOD_X_TILED: > case I915_FORMAT_MOD_Y_TILED: > + case I915_FORMAT_MOD_4_TILED: > break; > default: > drm_dbg(&dev_priv->drm, > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c > index 28890876bdeb..e5cda5bcbde4 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier) > return PLANE_CTL_TILED_X; > case I915_FORMAT_MOD_Y_TILED: > return PLANE_CTL_TILED_Y; > + case I915_FORMAT_MOD_4_TILED: > + return PLANE_CTL_TILED_4; > case I915_FORMAT_MOD_Y_TILED_CCS: > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; > @@ -1971,9 +1973,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, > case DRM_FORMAT_Y216: > case DRM_FORMAT_XVYU12_16161616: > case DRM_FORMAT_XVYU16161616: > - if (modifier == DRM_FORMAT_MOD_LINEAR || > - modifier == I915_FORMAT_MOD_X_TILED || > - modifier == I915_FORMAT_MOD_Y_TILED) > + if (!intel_fb_is_ccs_modifier(modifier)) > return true; > fallthrough; > default: > @@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, > else > fb->modifier = I915_FORMAT_MOD_Y_TILED; > break; > - case PLANE_CTL_TILED_YF: > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; > - else > - fb->modifier = I915_FORMAT_MOD_Yf_TILED; > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */ To be safe, maybe add a static_assert(PLANE_CTL_TILED_YF == PLANE_CTL_TILED_4); ? > + if (HAS_4TILE(dev_priv)) { > + fb->modifier = I915_FORMAT_MOD_4_TILED; > + } else { > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; > + else > + fb->modifier = I915_FORMAT_MOD_Yf_TILED; > + } > break; > default: > MISSING_CASE(tiling); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 1bfadd9127fc..3d90bd732e91 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7) > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) > +#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile) > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6) > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index f01cba4ec283..403d3a581ce7 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -1044,6 +1044,7 @@ static const struct intel_device_info dg2_info = { > DGFX_FEATURES, > .graphics.rel = 55, > .media.rel = 55, > + .has_4tile = 1, > PLATFORM(INTEL_DG2), > .platform_engine_mask = > BIT(RCS0) | BIT(BCS0) | > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 3450818802c2..22d18a292430 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7284,6 +7284,7 @@ enum { > #define PLANE_CTL_TILED_X (1 << 10) > #define PLANE_CTL_TILED_Y (4 << 10) > #define PLANE_CTL_TILED_YF (5 << 10) > +#define PLANE_CTL_TILED_4 (5 << 10) > #define PLANE_CTL_ASYNC_FLIP (1 << 9) > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8) > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */ > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index 669f0d26c3c3..67177e18704a 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -125,6 +125,7 @@ enum intel_ppgtt_type { > func(has_64bit_reloc); \ > func(gpu_reset_clobbers_display); \ > func(has_reset_engine); \ > + func(has_4tile); \ > func(has_global_mocs); \ > func(has_gt_uc); \ > func(has_l3_dpf); \ > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 01fa3fac1b57..167704f0acf0 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state, > } > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED || > + modifier == I915_FORMAT_MOD_4_TILED || > modifier == I915_FORMAT_MOD_Yf_TILED || > modifier == I915_FORMAT_MOD_Y_TILED_CCS || > modifier == I915_FORMAT_MOD_Yf_TILED_CCS; > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h > index 7f652c96845b..41184a94935d 100644 > --- a/include/uapi/drm/drm_fourcc.h > +++ b/include/uapi/drm/drm_fourcc.h > @@ -564,6 +564,14 @@ extern "C" { > * pitch is required to be a multiple of 4 tile widths. > */ > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) > +/* > + * Intel F-tiling(aka Tile4) layout > + * v4 and v5 attempted to get rid of the F-tile references, but this was left behind. > + * This is a tiled layout using 4Kb tiles in row-major layout. > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD > + * (16 bytes) chunks column-major.. I can't picture how tile 4 is organized from this description. Could we update it? Here's a draft I came up with when wondering how I might do this myself: * This is a tiled layout using 4KB tiles in a row-major layout. It has the same * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It * only differs from Tile Y at the 256B granularity in between. At this * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape * of 64B x 8 rows. -Nanley > + */ > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9) > > /* > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks > -- > 2.24.1.485.gad05a3d8e5 >
On Mon, Nov 22, 2021 at 05:08:31PM -0500, Nanley Chery wrote: > Hi Stanislav, > > Are there IGT tests for this modifier? Hi Nanley Yes, there should be plenty of those, not sure they are all sent to upstream though. We have a separate team doing this. That modifier should be added to kms_plane_multiple and many others Stan > > On Mon, Nov 22, 2021 at 4:14 PM Stanislav Lisovskiy > <stanislav.lisovskiy@intel.com> wrote: > > > > TileF(Tile4 in bspec) format is 4K tile organized into > > 64B subtiles with same basic shape as for legacy TileY > > which will be supported by Display13. > > > > v2: - Fixed wrong case condition(Jani Nikula) > > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak) > > > > v3: - s/I915_TILING_F/TILING_4/g > > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g > > - Removed unneeded fencing code > > > > v4: - Rebased, fixed merge conflict with new table-oriented > > format modifier checking(Stan) > > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan) > > > > v5: - Still had to remove some Tile F mentionings > > - Moved has_4tile from adlp to DG2(Ramalingam C) > > - Check specifically for DG2, but not the Display13(Imre) > > > > v6: - Moved Tile4 assocating struct for modifier/display to > > the beginning(Imre Deak) > > - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier > > checks(Imre Deak) > > - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12 > > (Imre Deak) > > > > v7: - Fixed display_ver to { 13, 13 }(Imre Deak) > > - Removed redundant newline(Imre Deak) > > > > Reviewed-by: Imre Deak <imre.deak@intel.com> > > Cc: Imre Deak <imre.deak@intel.com> > > Cc: Matt Roper <matthew.d.roper@intel.com> > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 1 + > > drivers/gpu/drm/i915/display/intel_fb.c | 9 +++++++++ > > drivers/gpu/drm/i915/display/intel_fbc.c | 1 + > > .../drm/i915/display/intel_plane_initial.c | 1 + > > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++-------- > > drivers/gpu/drm/i915/i915_drv.h | 1 + > > drivers/gpu/drm/i915/i915_pci.c | 1 + > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > drivers/gpu/drm/i915/intel_device_info.h | 1 + > > drivers/gpu/drm/i915/intel_pm.c | 1 + > > include/uapi/drm/drm_fourcc.h | 8 ++++++++ > > 11 files changed, 37 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index f3c9208a30b1..7429965d3682 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int > > case I915_FORMAT_MOD_X_TILED: > > case I915_FORMAT_MOD_Y_TILED: > > case I915_FORMAT_MOD_Yf_TILED: > > + case I915_FORMAT_MOD_4_TILED: > > break; > > default: > > drm_dbg_kms(&i915->drm, > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c > > index c4a743d0913f..b7f1ef62072c 100644 > > --- a/drivers/gpu/drm/i915/display/intel_fb.c > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c > > @@ -139,6 +139,9 @@ struct intel_modifier_desc { > > > > static const struct intel_modifier_desc intel_modifiers[] = { > > { > > + .modifier = I915_FORMAT_MOD_4_TILED, > > + .display_ver = { 13, 13 }, > > I see that every other modifier has the plane_cap field set. Why is it > okay for it to be zero here? > > > + }, { > > .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, > > .display_ver = { 12, 13 }, > > .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC, > > @@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) > > return 128; > > else > > return 512; > > + case I915_FORMAT_MOD_4_TILED: > > + /* > > + * Each 4K tile consists of 64B(8*8) subtiles, with > > + * same shape as Y Tile(i.e 4*16B OWords) > > + */ > > + return 128; > > case I915_FORMAT_MOD_Y_TILED_CCS: > > if (intel_fb_is_ccs_aux_plane(fb, color_plane)) > > return 128; > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > > index d0c34bc3af6c..0ceabe40d8c9 100644 > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > @@ -898,6 +898,7 @@ static bool tiling_is_valid(struct drm_i915_private *i915, > > case I915_FORMAT_MOD_Y_TILED: > > case I915_FORMAT_MOD_Yf_TILED: > > return DISPLAY_VER(i915) >= 9; > > + case I915_FORMAT_MOD_4_TILED: > > The tile Y cases above check the display version. Should we do the same here? > > > case I915_FORMAT_MOD_X_TILED: > > return true; > > default: > > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c > > index dcd698a02da2..d80855ee9b96 100644 > > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c > > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c > > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc, > > case DRM_FORMAT_MOD_LINEAR: > > case I915_FORMAT_MOD_X_TILED: > > case I915_FORMAT_MOD_Y_TILED: > > + case I915_FORMAT_MOD_4_TILED: > > break; > > default: > > drm_dbg(&dev_priv->drm, > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c > > index 28890876bdeb..e5cda5bcbde4 100644 > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier) > > return PLANE_CTL_TILED_X; > > case I915_FORMAT_MOD_Y_TILED: > > return PLANE_CTL_TILED_Y; > > + case I915_FORMAT_MOD_4_TILED: > > + return PLANE_CTL_TILED_4; > > case I915_FORMAT_MOD_Y_TILED_CCS: > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; > > @@ -1971,9 +1973,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, > > case DRM_FORMAT_Y216: > > case DRM_FORMAT_XVYU12_16161616: > > case DRM_FORMAT_XVYU16161616: > > - if (modifier == DRM_FORMAT_MOD_LINEAR || > > - modifier == I915_FORMAT_MOD_X_TILED || > > - modifier == I915_FORMAT_MOD_Y_TILED) > > + if (!intel_fb_is_ccs_modifier(modifier)) > > return true; > > fallthrough; > > default: > > @@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, > > else > > fb->modifier = I915_FORMAT_MOD_Y_TILED; > > break; > > - case PLANE_CTL_TILED_YF: > > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; > > - else > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED; > > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */ > > To be safe, maybe add a static_assert(PLANE_CTL_TILED_YF == > PLANE_CTL_TILED_4); ? > > > + if (HAS_4TILE(dev_priv)) { > > + fb->modifier = I915_FORMAT_MOD_4_TILED; > > + } else { > > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; > > + else > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED; > > + } > > break; > > default: > > MISSING_CASE(tiling); > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > index 1bfadd9127fc..3d90bd732e91 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7) > > > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) > > +#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile) > > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) > > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) > > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6) > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > > index f01cba4ec283..403d3a581ce7 100644 > > --- a/drivers/gpu/drm/i915/i915_pci.c > > +++ b/drivers/gpu/drm/i915/i915_pci.c > > @@ -1044,6 +1044,7 @@ static const struct intel_device_info dg2_info = { > > DGFX_FEATURES, > > .graphics.rel = 55, > > .media.rel = 55, > > + .has_4tile = 1, > > PLATFORM(INTEL_DG2), > > .platform_engine_mask = > > BIT(RCS0) | BIT(BCS0) | > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 3450818802c2..22d18a292430 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -7284,6 +7284,7 @@ enum { > > #define PLANE_CTL_TILED_X (1 << 10) > > #define PLANE_CTL_TILED_Y (4 << 10) > > #define PLANE_CTL_TILED_YF (5 << 10) > > +#define PLANE_CTL_TILED_4 (5 << 10) > > #define PLANE_CTL_ASYNC_FLIP (1 << 9) > > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8) > > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */ > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > > index 669f0d26c3c3..67177e18704a 100644 > > --- a/drivers/gpu/drm/i915/intel_device_info.h > > +++ b/drivers/gpu/drm/i915/intel_device_info.h > > @@ -125,6 +125,7 @@ enum intel_ppgtt_type { > > func(has_64bit_reloc); \ > > func(gpu_reset_clobbers_display); \ > > func(has_reset_engine); \ > > + func(has_4tile); \ > > func(has_global_mocs); \ > > func(has_gt_uc); \ > > func(has_l3_dpf); \ > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index 01fa3fac1b57..167704f0acf0 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state, > > } > > > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED || > > + modifier == I915_FORMAT_MOD_4_TILED || > > modifier == I915_FORMAT_MOD_Yf_TILED || > > modifier == I915_FORMAT_MOD_Y_TILED_CCS || > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS; > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h > > index 7f652c96845b..41184a94935d 100644 > > --- a/include/uapi/drm/drm_fourcc.h > > +++ b/include/uapi/drm/drm_fourcc.h > > @@ -564,6 +564,14 @@ extern "C" { > > * pitch is required to be a multiple of 4 tile widths. > > */ > > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) > > +/* > > + * Intel F-tiling(aka Tile4) layout > > + * > > v4 and v5 attempted to get rid of the F-tile references, but this was > left behind. > > > + * This is a tiled layout using 4Kb tiles in row-major layout. > > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD > > + * (16 bytes) chunks column-major.. > > I can't picture how tile 4 is organized from this description. Could > we update it? > Here's a draft I came up with when wondering how I might do this myself: > > * This is a tiled layout using 4KB tiles in a row-major layout. It has the same > * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It > * only differs from Tile Y at the 256B granularity in between. At this > * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape > * of 64B x 8 rows. > > -Nanley > > > + */ > > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9) > > > > /* > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks > > -- > > 2.24.1.485.gad05a3d8e5 > >
> -----Original Message----- > From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com> > Sent: Tuesday, November 23, 2021 3:14 AM > To: Nanley Chery <nanleychery@gmail.com> > Cc: intel-gfx@lists.freedesktop.org; Chery, Nanley G > <nanley.g.chery@intel.com> > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support > > On Mon, Nov 22, 2021 at 05:08:31PM -0500, Nanley Chery wrote: > > Hi Stanislav, > > > > Are there IGT tests for this modifier? > > Hi Nanley > > Yes, there should be plenty of those, not sure they > are all sent to upstream though. > We have a separate team doing this. > That modifier should be added to kms_plane_multiple > and many others > Okay, I'll be on the lookout for them. > Stan > Looks like you missed the other review comments I left in my prior email. -Nanley > > > > On Mon, Nov 22, 2021 at 4:14 PM Stanislav Lisovskiy > > <stanislav.lisovskiy@intel.com> wrote: > > > > > > TileF(Tile4 in bspec) format is 4K tile organized into > > > 64B subtiles with same basic shape as for legacy TileY > > > which will be supported by Display13. > > > > > > v2: - Fixed wrong case condition(Jani Nikula) > > > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak) > > > > > > v3: - s/I915_TILING_F/TILING_4/g > > > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g > > > - Removed unneeded fencing code > > > > > > v4: - Rebased, fixed merge conflict with new table-oriented > > > format modifier checking(Stan) > > > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan) > > > > > > v5: - Still had to remove some Tile F mentionings > > > - Moved has_4tile from adlp to DG2(Ramalingam C) > > > - Check specifically for DG2, but not the Display13(Imre) > > > > > > v6: - Moved Tile4 assocating struct for modifier/display to > > > the beginning(Imre Deak) > > > - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier > > > checks(Imre Deak) > > > - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12 > > > (Imre Deak) > > > > > > v7: - Fixed display_ver to { 13, 13 }(Imre Deak) > > > - Removed redundant newline(Imre Deak) > > > > > > Reviewed-by: Imre Deak <imre.deak@intel.com> > > > Cc: Imre Deak <imre.deak@intel.com> > > > Cc: Matt Roper <matthew.d.roper@intel.com> > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > > > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_display.c | 1 + > > > drivers/gpu/drm/i915/display/intel_fb.c | 9 +++++++++ > > > drivers/gpu/drm/i915/display/intel_fbc.c | 1 + > > > .../drm/i915/display/intel_plane_initial.c | 1 + > > > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++-------- > > > drivers/gpu/drm/i915/i915_drv.h | 1 + > > > drivers/gpu/drm/i915/i915_pci.c | 1 + > > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > > drivers/gpu/drm/i915/intel_device_info.h | 1 + > > > drivers/gpu/drm/i915/intel_pm.c | 1 + > > > include/uapi/drm/drm_fourcc.h | 8 ++++++++ > > > 11 files changed, 37 insertions(+), 8 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > > > index f3c9208a30b1..7429965d3682 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct > intel_atomic_state *state, struct int > > > case I915_FORMAT_MOD_X_TILED: > > > case I915_FORMAT_MOD_Y_TILED: > > > case I915_FORMAT_MOD_Yf_TILED: > > > + case I915_FORMAT_MOD_4_TILED: > > > break; > > > default: > > > drm_dbg_kms(&i915->drm, > > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c > b/drivers/gpu/drm/i915/display/intel_fb.c > > > index c4a743d0913f..b7f1ef62072c 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_fb.c > > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c > > > @@ -139,6 +139,9 @@ struct intel_modifier_desc { > > > > > > static const struct intel_modifier_desc intel_modifiers[] = { > > > { > > > + .modifier = I915_FORMAT_MOD_4_TILED, > > > + .display_ver = { 13, 13 }, > > > > I see that every other modifier has the plane_cap field set. Why is it > > okay for it to be zero here? > > > > > + }, { > > > .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, > > > .display_ver = { 12, 13 }, > > > .plane_caps = INTEL_PLANE_CAP_TILING_Y | > INTEL_PLANE_CAP_CCS_MC, > > > @@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct > drm_framebuffer *fb, int color_plane) > > > return 128; > > > else > > > return 512; > > > + case I915_FORMAT_MOD_4_TILED: > > > + /* > > > + * Each 4K tile consists of 64B(8*8) subtiles, with > > > + * same shape as Y Tile(i.e 4*16B OWords) > > > + */ > > > + return 128; > > > case I915_FORMAT_MOD_Y_TILED_CCS: > > > if (intel_fb_is_ccs_aux_plane(fb, color_plane)) > > > return 128; > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c > b/drivers/gpu/drm/i915/display/intel_fbc.c > > > index d0c34bc3af6c..0ceabe40d8c9 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > > @@ -898,6 +898,7 @@ static bool tiling_is_valid(struct drm_i915_private > *i915, > > > case I915_FORMAT_MOD_Y_TILED: > > > case I915_FORMAT_MOD_Yf_TILED: > > > return DISPLAY_VER(i915) >= 9; > > > + case I915_FORMAT_MOD_4_TILED: > > > > The tile Y cases above check the display version. Should we do the same here? > > > > > case I915_FORMAT_MOD_X_TILED: > > > return true; > > > default: > > > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c > b/drivers/gpu/drm/i915/display/intel_plane_initial.c > > > index dcd698a02da2..d80855ee9b96 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c > > > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c > > > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc, > > > case DRM_FORMAT_MOD_LINEAR: > > > case I915_FORMAT_MOD_X_TILED: > > > case I915_FORMAT_MOD_Y_TILED: > > > + case I915_FORMAT_MOD_4_TILED: > > > break; > > > default: > > > drm_dbg(&dev_priv->drm, > > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c > b/drivers/gpu/drm/i915/display/skl_universal_plane.c > > > index 28890876bdeb..e5cda5bcbde4 100644 > > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > > > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier) > > > return PLANE_CTL_TILED_X; > > > case I915_FORMAT_MOD_Y_TILED: > > > return PLANE_CTL_TILED_Y; > > > + case I915_FORMAT_MOD_4_TILED: > > > + return PLANE_CTL_TILED_4; > > > case I915_FORMAT_MOD_Y_TILED_CCS: > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > > return PLANE_CTL_TILED_Y | > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; > > > @@ -1971,9 +1973,7 @@ static bool > gen12_plane_format_mod_supported(struct drm_plane *_plane, > > > case DRM_FORMAT_Y216: > > > case DRM_FORMAT_XVYU12_16161616: > > > case DRM_FORMAT_XVYU16161616: > > > - if (modifier == DRM_FORMAT_MOD_LINEAR || > > > - modifier == I915_FORMAT_MOD_X_TILED || > > > - modifier == I915_FORMAT_MOD_Y_TILED) > > > + if (!intel_fb_is_ccs_modifier(modifier)) > > > return true; > > > fallthrough; > > > default: > > > @@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct intel_crtc > *crtc, > > > else > > > fb->modifier = I915_FORMAT_MOD_Y_TILED; > > > break; > > > - case PLANE_CTL_TILED_YF: > > > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; > > > - else > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED; > > > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */ > > > > To be safe, maybe add a static_assert(PLANE_CTL_TILED_YF == > > PLANE_CTL_TILED_4); ? > > > > > + if (HAS_4TILE(dev_priv)) { > > > + fb->modifier = I915_FORMAT_MOD_4_TILED; > > > + } else { > > > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; > > > + else > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED; > > > + } > > > break; > > > default: > > > MISSING_CASE(tiling); > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h > b/drivers/gpu/drm/i915/i915_drv.h > > > index 1bfadd9127fc..3d90bd732e91 100644 > > > --- a/drivers/gpu/drm/i915/i915_drv.h > > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private > *i915, > > > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7) > > > > > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) > > > +#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile) > > > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) > > > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) > > > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6) > > > diff --git a/drivers/gpu/drm/i915/i915_pci.c > b/drivers/gpu/drm/i915/i915_pci.c > > > index f01cba4ec283..403d3a581ce7 100644 > > > --- a/drivers/gpu/drm/i915/i915_pci.c > > > +++ b/drivers/gpu/drm/i915/i915_pci.c > > > @@ -1044,6 +1044,7 @@ static const struct intel_device_info dg2_info = { > > > DGFX_FEATURES, > > > .graphics.rel = 55, > > > .media.rel = 55, > > > + .has_4tile = 1, > > > PLATFORM(INTEL_DG2), > > > .platform_engine_mask = > > > BIT(RCS0) | BIT(BCS0) | > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > > > index 3450818802c2..22d18a292430 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -7284,6 +7284,7 @@ enum { > > > #define PLANE_CTL_TILED_X (1 << 10) > > > #define PLANE_CTL_TILED_Y (4 << 10) > > > #define PLANE_CTL_TILED_YF (5 << 10) > > > +#define PLANE_CTL_TILED_4 (5 << 10) > > > #define PLANE_CTL_ASYNC_FLIP (1 << 9) > > > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8) > > > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */ > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h > b/drivers/gpu/drm/i915/intel_device_info.h > > > index 669f0d26c3c3..67177e18704a 100644 > > > --- a/drivers/gpu/drm/i915/intel_device_info.h > > > +++ b/drivers/gpu/drm/i915/intel_device_info.h > > > @@ -125,6 +125,7 @@ enum intel_ppgtt_type { > > > func(has_64bit_reloc); \ > > > func(gpu_reset_clobbers_display); \ > > > func(has_reset_engine); \ > > > + func(has_4tile); \ > > > func(has_global_mocs); \ > > > func(has_gt_uc); \ > > > func(has_l3_dpf); \ > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > b/drivers/gpu/drm/i915/intel_pm.c > > > index 01fa3fac1b57..167704f0acf0 100644 > > > --- a/drivers/gpu/drm/i915/intel_pm.c > > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > > @@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct > intel_crtc_state *crtc_state, > > > } > > > > > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED || > > > + modifier == I915_FORMAT_MOD_4_TILED || > > > modifier == I915_FORMAT_MOD_Yf_TILED || > > > modifier == I915_FORMAT_MOD_Y_TILED_CCS || > > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS; > > > diff --git a/include/uapi/drm/drm_fourcc.h > b/include/uapi/drm/drm_fourcc.h > > > index 7f652c96845b..41184a94935d 100644 > > > --- a/include/uapi/drm/drm_fourcc.h > > > +++ b/include/uapi/drm/drm_fourcc.h > > > @@ -564,6 +564,14 @@ extern "C" { > > > * pitch is required to be a multiple of 4 tile widths. > > > */ > > > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC > fourcc_mod_code(INTEL, 8) > > > +/* > > > + * Intel F-tiling(aka Tile4) layout > > > + * > > > > v4 and v5 attempted to get rid of the F-tile references, but this was > > left behind. > > > > > + * This is a tiled layout using 4Kb tiles in row-major layout. > > > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD > > > + * (16 bytes) chunks column-major.. > > > > I can't picture how tile 4 is organized from this description. Could > > we update it? > > Here's a draft I came up with when wondering how I might do this myself: > > > > * This is a tiled layout using 4KB tiles in a row-major layout. It has the same > > * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It > > * only differs from Tile Y at the 256B granularity in between. At this > > * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape > > * of 64B x 8 rows. > > > > -Nanley > > > > > + */ > > > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9) > > > > > > /* > > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks > > > -- > > > 2.24.1.485.gad05a3d8e5 > > >
On Tue, Nov 23, 2021 at 02:41:20PM +0200, Chery, Nanley G wrote: > > > > -----Original Message----- > > From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com> > > Sent: Tuesday, November 23, 2021 3:14 AM > > To: Nanley Chery <nanleychery@gmail.com> > > Cc: intel-gfx@lists.freedesktop.org; Chery, Nanley G > > <nanley.g.chery@intel.com> > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support > > > > On Mon, Nov 22, 2021 at 05:08:31PM -0500, Nanley Chery wrote: > > > Hi Stanislav, > > > > > > Are there IGT tests for this modifier? > > > > Hi Nanley > > > > Yes, there should be plenty of those, not sure they > > are all sent to upstream though. > > We have a separate team doing this. > > That modifier should be added to kms_plane_multiple > > and many others > > > > Okay, I'll be on the lookout for them. > > > Stan > > > > Looks like you missed the other review comments I left in my prior email. Oh, sorry just saw those. I pushed this already, I will check those anyway and sent additional patch, if needed. Stan > > -Nanley > > > > > > > On Mon, Nov 22, 2021 at 4:14 PM Stanislav Lisovskiy > > > <stanislav.lisovskiy@intel.com> wrote: > > > > > > > > TileF(Tile4 in bspec) format is 4K tile organized into > > > > 64B subtiles with same basic shape as for legacy TileY > > > > which will be supported by Display13. > > > > > > > > v2: - Fixed wrong case condition(Jani Nikula) > > > > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak) > > > > > > > > v3: - s/I915_TILING_F/TILING_4/g > > > > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g > > > > - Removed unneeded fencing code > > > > > > > > v4: - Rebased, fixed merge conflict with new table-oriented > > > > format modifier checking(Stan) > > > > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan) > > > > > > > > v5: - Still had to remove some Tile F mentionings > > > > - Moved has_4tile from adlp to DG2(Ramalingam C) > > > > - Check specifically for DG2, but not the Display13(Imre) > > > > > > > > v6: - Moved Tile4 assocating struct for modifier/display to > > > > the beginning(Imre Deak) > > > > - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier > > > > checks(Imre Deak) > > > > - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12 > > > > (Imre Deak) > > > > > > > > v7: - Fixed display_ver to { 13, 13 }(Imre Deak) > > > > - Removed redundant newline(Imre Deak) > > > > > > > > Reviewed-by: Imre Deak <imre.deak@intel.com> > > > > Cc: Imre Deak <imre.deak@intel.com> > > > > Cc: Matt Roper <matthew.d.roper@intel.com> > > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > > > > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_display.c | 1 + > > > > drivers/gpu/drm/i915/display/intel_fb.c | 9 +++++++++ > > > > drivers/gpu/drm/i915/display/intel_fbc.c | 1 + > > > > .../drm/i915/display/intel_plane_initial.c | 1 + > > > > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++-------- > > > > drivers/gpu/drm/i915/i915_drv.h | 1 + > > > > drivers/gpu/drm/i915/i915_pci.c | 1 + > > > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > > > drivers/gpu/drm/i915/intel_device_info.h | 1 + > > > > drivers/gpu/drm/i915/intel_pm.c | 1 + > > > > include/uapi/drm/drm_fourcc.h | 8 ++++++++ > > > > 11 files changed, 37 insertions(+), 8 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > b/drivers/gpu/drm/i915/display/intel_display.c > > > > index f3c9208a30b1..7429965d3682 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > > @@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct > > intel_atomic_state *state, struct int > > > > case I915_FORMAT_MOD_X_TILED: > > > > case I915_FORMAT_MOD_Y_TILED: > > > > case I915_FORMAT_MOD_Yf_TILED: > > > > + case I915_FORMAT_MOD_4_TILED: > > > > break; > > > > default: > > > > drm_dbg_kms(&i915->drm, > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c > > b/drivers/gpu/drm/i915/display/intel_fb.c > > > > index c4a743d0913f..b7f1ef62072c 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_fb.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c > > > > @@ -139,6 +139,9 @@ struct intel_modifier_desc { > > > > > > > > static const struct intel_modifier_desc intel_modifiers[] = { > > > > { > > > > + .modifier = I915_FORMAT_MOD_4_TILED, > > > > + .display_ver = { 13, 13 }, > > > > > > I see that every other modifier has the plane_cap field set. Why is it > > > okay for it to be zero here? > > > > > > > + }, { > > > > .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, > > > > .display_ver = { 12, 13 }, > > > > .plane_caps = INTEL_PLANE_CAP_TILING_Y | > > INTEL_PLANE_CAP_CCS_MC, > > > > @@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct > > drm_framebuffer *fb, int color_plane) > > > > return 128; > > > > else > > > > return 512; > > > > + case I915_FORMAT_MOD_4_TILED: > > > > + /* > > > > + * Each 4K tile consists of 64B(8*8) subtiles, with > > > > + * same shape as Y Tile(i.e 4*16B OWords) > > > > + */ > > > > + return 128; > > > > case I915_FORMAT_MOD_Y_TILED_CCS: > > > > if (intel_fb_is_ccs_aux_plane(fb, color_plane)) > > > > return 128; > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c > > b/drivers/gpu/drm/i915/display/intel_fbc.c > > > > index d0c34bc3af6c..0ceabe40d8c9 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > > > @@ -898,6 +898,7 @@ static bool tiling_is_valid(struct drm_i915_private > > *i915, > > > > case I915_FORMAT_MOD_Y_TILED: > > > > case I915_FORMAT_MOD_Yf_TILED: > > > > return DISPLAY_VER(i915) >= 9; > > > > + case I915_FORMAT_MOD_4_TILED: > > > > > > The tile Y cases above check the display version. Should we do the same here? > > > > > > > case I915_FORMAT_MOD_X_TILED: > > > > return true; > > > > default: > > > > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c > > b/drivers/gpu/drm/i915/display/intel_plane_initial.c > > > > index dcd698a02da2..d80855ee9b96 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c > > > > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc, > > > > case DRM_FORMAT_MOD_LINEAR: > > > > case I915_FORMAT_MOD_X_TILED: > > > > case I915_FORMAT_MOD_Y_TILED: > > > > + case I915_FORMAT_MOD_4_TILED: > > > > break; > > > > default: > > > > drm_dbg(&dev_priv->drm, > > > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c > > b/drivers/gpu/drm/i915/display/skl_universal_plane.c > > > > index 28890876bdeb..e5cda5bcbde4 100644 > > > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > > > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > > > > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier) > > > > return PLANE_CTL_TILED_X; > > > > case I915_FORMAT_MOD_Y_TILED: > > > > return PLANE_CTL_TILED_Y; > > > > + case I915_FORMAT_MOD_4_TILED: > > > > + return PLANE_CTL_TILED_4; > > > > case I915_FORMAT_MOD_Y_TILED_CCS: > > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > > > return PLANE_CTL_TILED_Y | > > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; > > > > @@ -1971,9 +1973,7 @@ static bool > > gen12_plane_format_mod_supported(struct drm_plane *_plane, > > > > case DRM_FORMAT_Y216: > > > > case DRM_FORMAT_XVYU12_16161616: > > > > case DRM_FORMAT_XVYU16161616: > > > > - if (modifier == DRM_FORMAT_MOD_LINEAR || > > > > - modifier == I915_FORMAT_MOD_X_TILED || > > > > - modifier == I915_FORMAT_MOD_Y_TILED) > > > > + if (!intel_fb_is_ccs_modifier(modifier)) > > > > return true; > > > > fallthrough; > > > > default: > > > > @@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct intel_crtc > > *crtc, > > > > else > > > > fb->modifier = I915_FORMAT_MOD_Y_TILED; > > > > break; > > > > - case PLANE_CTL_TILED_YF: > > > > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; > > > > - else > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED; > > > > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */ > > > > > > To be safe, maybe add a static_assert(PLANE_CTL_TILED_YF == > > > PLANE_CTL_TILED_4); ? > > > > > > > + if (HAS_4TILE(dev_priv)) { > > > > + fb->modifier = I915_FORMAT_MOD_4_TILED; > > > > + } else { > > > > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) > > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; > > > > + else > > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED; > > > > + } > > > > break; > > > > default: > > > > MISSING_CASE(tiling); > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h > > b/drivers/gpu/drm/i915/i915_drv.h > > > > index 1bfadd9127fc..3d90bd732e91 100644 > > > > --- a/drivers/gpu/drm/i915/i915_drv.h > > > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > > > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private > > *i915, > > > > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7) > > > > > > > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) > > > > +#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile) > > > > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) > > > > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) > > > > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6) > > > > diff --git a/drivers/gpu/drm/i915/i915_pci.c > > b/drivers/gpu/drm/i915/i915_pci.c > > > > index f01cba4ec283..403d3a581ce7 100644 > > > > --- a/drivers/gpu/drm/i915/i915_pci.c > > > > +++ b/drivers/gpu/drm/i915/i915_pci.c > > > > @@ -1044,6 +1044,7 @@ static const struct intel_device_info dg2_info = { > > > > DGFX_FEATURES, > > > > .graphics.rel = 55, > > > > .media.rel = 55, > > > > + .has_4tile = 1, > > > > PLATFORM(INTEL_DG2), > > > > .platform_engine_mask = > > > > BIT(RCS0) | BIT(BCS0) | > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > > > index 3450818802c2..22d18a292430 100644 > > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > > @@ -7284,6 +7284,7 @@ enum { > > > > #define PLANE_CTL_TILED_X (1 << 10) > > > > #define PLANE_CTL_TILED_Y (4 << 10) > > > > #define PLANE_CTL_TILED_YF (5 << 10) > > > > +#define PLANE_CTL_TILED_4 (5 << 10) > > > > #define PLANE_CTL_ASYNC_FLIP (1 << 9) > > > > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8) > > > > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */ > > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h > > b/drivers/gpu/drm/i915/intel_device_info.h > > > > index 669f0d26c3c3..67177e18704a 100644 > > > > --- a/drivers/gpu/drm/i915/intel_device_info.h > > > > +++ b/drivers/gpu/drm/i915/intel_device_info.h > > > > @@ -125,6 +125,7 @@ enum intel_ppgtt_type { > > > > func(has_64bit_reloc); \ > > > > func(gpu_reset_clobbers_display); \ > > > > func(has_reset_engine); \ > > > > + func(has_4tile); \ > > > > func(has_global_mocs); \ > > > > func(has_gt_uc); \ > > > > func(has_l3_dpf); \ > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > b/drivers/gpu/drm/i915/intel_pm.c > > > > index 01fa3fac1b57..167704f0acf0 100644 > > > > --- a/drivers/gpu/drm/i915/intel_pm.c > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > > > @@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct > > intel_crtc_state *crtc_state, > > > > } > > > > > > > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED || > > > > + modifier == I915_FORMAT_MOD_4_TILED || > > > > modifier == I915_FORMAT_MOD_Yf_TILED || > > > > modifier == I915_FORMAT_MOD_Y_TILED_CCS || > > > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS; > > > > diff --git a/include/uapi/drm/drm_fourcc.h > > b/include/uapi/drm/drm_fourcc.h > > > > index 7f652c96845b..41184a94935d 100644 > > > > --- a/include/uapi/drm/drm_fourcc.h > > > > +++ b/include/uapi/drm/drm_fourcc.h > > > > @@ -564,6 +564,14 @@ extern "C" { > > > > * pitch is required to be a multiple of 4 tile widths. > > > > */ > > > > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC > > fourcc_mod_code(INTEL, 8) > > > > +/* > > > > + * Intel F-tiling(aka Tile4) layout > > > > + * > > > > > > v4 and v5 attempted to get rid of the F-tile references, but this was > > > left behind. > > > > > > > + * This is a tiled layout using 4Kb tiles in row-major layout. > > > > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD > > > > + * (16 bytes) chunks column-major.. > > > > > > I can't picture how tile 4 is organized from this description. Could > > > we update it? > > > Here's a draft I came up with when wondering how I might do this myself: > > > > > > * This is a tiled layout using 4KB tiles in a row-major layout. It has the same > > > * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It > > > * only differs from Tile Y at the 256B granularity in between. At this > > > * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape > > > * of 64B x 8 rows. > > > > > > -Nanley > > > > > > > + */ > > > > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9) > > > > > > > > /* > > > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks > > > > -- > > > > 2.24.1.485.gad05a3d8e5 > > > >
> -----Original Message----- > From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com> > Sent: Tuesday, November 23, 2021 8:37 AM > To: Chery, Nanley G <nanley.g.chery@intel.com> > Cc: Nanley Chery <nanleychery@gmail.com>; intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support > > On Tue, Nov 23, 2021 at 02:41:20PM +0200, Chery, Nanley G wrote: > > > > > > > -----Original Message----- > > > From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com> > > > Sent: Tuesday, November 23, 2021 3:14 AM > > > To: Nanley Chery <nanleychery@gmail.com> > > > Cc: intel-gfx@lists.freedesktop.org; Chery, Nanley G > > > <nanley.g.chery@intel.com> > > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format > > > support > > > > > > On Mon, Nov 22, 2021 at 05:08:31PM -0500, Nanley Chery wrote: > > > > Hi Stanislav, > > > > > > > > Are there IGT tests for this modifier? > > > > > > Hi Nanley > > > > > > Yes, there should be plenty of those, not sure they are all sent to > > > upstream though. > > > We have a separate team doing this. > > > That modifier should be added to kms_plane_multiple and many others > > > > > > > Okay, I'll be on the lookout for them. > > > > > Stan > > > > > > > Looks like you missed the other review comments I left in my prior email. > > Oh, sorry just saw those. I pushed this already, I will check those anyway > and sent additional patch, if needed. > Where has this been pushed to? We're still requiring an Ack from userspace/mesa to get new modifiers upstream, right? -Nanley > Stan > > > > > -Nanley > > > > > > > > > > On Mon, Nov 22, 2021 at 4:14 PM Stanislav Lisovskiy > > > > <stanislav.lisovskiy@intel.com> wrote: > > > > > > > > > > TileF(Tile4 in bspec) format is 4K tile organized into > > > > > 64B subtiles with same basic shape as for legacy TileY > > > > > which will be supported by Display13. > > > > > > > > > > v2: - Fixed wrong case condition(Jani Nikula) > > > > > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak) > > > > > > > > > > v3: - s/I915_TILING_F/TILING_4/g > > > > > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g > > > > > - Removed unneeded fencing code > > > > > > > > > > v4: - Rebased, fixed merge conflict with new table-oriented > > > > > format modifier checking(Stan) > > > > > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan) > > > > > > > > > > v5: - Still had to remove some Tile F mentionings > > > > > - Moved has_4tile from adlp to DG2(Ramalingam C) > > > > > - Check specifically for DG2, but not the Display13(Imre) > > > > > > > > > > v6: - Moved Tile4 assocating struct for modifier/display to > > > > > the beginning(Imre Deak) > > > > > - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier > > > > > checks(Imre Deak) > > > > > - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12 > > > > > (Imre Deak) > > > > > > > > > > v7: - Fixed display_ver to { 13, 13 }(Imre Deak) > > > > > - Removed redundant newline(Imre Deak) > > > > > > > > > > Reviewed-by: Imre Deak <imre.deak@intel.com> > > > > > Cc: Imre Deak <imre.deak@intel.com> > > > > > Cc: Matt Roper <matthew.d.roper@intel.com> > > > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > > > > > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com> > > > > > --- > > > > > drivers/gpu/drm/i915/display/intel_display.c | 1 + > > > > > drivers/gpu/drm/i915/display/intel_fb.c | 9 +++++++++ > > > > > drivers/gpu/drm/i915/display/intel_fbc.c | 1 + > > > > > .../drm/i915/display/intel_plane_initial.c | 1 + > > > > > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++-------- > > > > > drivers/gpu/drm/i915/i915_drv.h | 1 + > > > > > drivers/gpu/drm/i915/i915_pci.c | 1 + > > > > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > > > > drivers/gpu/drm/i915/intel_device_info.h | 1 + > > > > > drivers/gpu/drm/i915/intel_pm.c | 1 + > > > > > include/uapi/drm/drm_fourcc.h | 8 ++++++++ > > > > > 11 files changed, 37 insertions(+), 8 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > > b/drivers/gpu/drm/i915/display/intel_display.c > > > > > index f3c9208a30b1..7429965d3682 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > > > @@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct > > > intel_atomic_state *state, struct int > > > > > case I915_FORMAT_MOD_X_TILED: > > > > > case I915_FORMAT_MOD_Y_TILED: > > > > > case I915_FORMAT_MOD_Yf_TILED: > > > > > + case I915_FORMAT_MOD_4_TILED: > > > > > break; > > > > > default: > > > > > drm_dbg_kms(&i915->drm, > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c > > > b/drivers/gpu/drm/i915/display/intel_fb.c > > > > > index c4a743d0913f..b7f1ef62072c 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_fb.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c > > > > > @@ -139,6 +139,9 @@ struct intel_modifier_desc { > > > > > > > > > > static const struct intel_modifier_desc intel_modifiers[] = { > > > > > { > > > > > + .modifier = I915_FORMAT_MOD_4_TILED, > > > > > + .display_ver = { 13, 13 }, > > > > > > > > I see that every other modifier has the plane_cap field set. Why is it > > > > okay for it to be zero here? > > > > > > > > > + }, { > > > > > .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, > > > > > .display_ver = { 12, 13 }, > > > > > .plane_caps = INTEL_PLANE_CAP_TILING_Y | > > > INTEL_PLANE_CAP_CCS_MC, > > > > > @@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct > > > drm_framebuffer *fb, int color_plane) > > > > > return 128; > > > > > else > > > > > return 512; > > > > > + case I915_FORMAT_MOD_4_TILED: > > > > > + /* > > > > > + * Each 4K tile consists of 64B(8*8) subtiles, with > > > > > + * same shape as Y Tile(i.e 4*16B OWords) > > > > > + */ > > > > > + return 128; > > > > > case I915_FORMAT_MOD_Y_TILED_CCS: > > > > > if (intel_fb_is_ccs_aux_plane(fb, color_plane)) > > > > > return 128; > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c > > > b/drivers/gpu/drm/i915/display/intel_fbc.c > > > > > index d0c34bc3af6c..0ceabe40d8c9 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > > > > @@ -898,6 +898,7 @@ static bool tiling_is_valid(struct > drm_i915_private > > > *i915, > > > > > case I915_FORMAT_MOD_Y_TILED: > > > > > case I915_FORMAT_MOD_Yf_TILED: > > > > > return DISPLAY_VER(i915) >= 9; > > > > > + case I915_FORMAT_MOD_4_TILED: > > > > > > > > The tile Y cases above check the display version. Should we do the same > here? > > > > > > > > > case I915_FORMAT_MOD_X_TILED: > > > > > return true; > > > > > default: > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c > > > b/drivers/gpu/drm/i915/display/intel_plane_initial.c > > > > > index dcd698a02da2..d80855ee9b96 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c > > > > > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc > *crtc, > > > > > case DRM_FORMAT_MOD_LINEAR: > > > > > case I915_FORMAT_MOD_X_TILED: > > > > > case I915_FORMAT_MOD_Y_TILED: > > > > > + case I915_FORMAT_MOD_4_TILED: > > > > > break; > > > > > default: > > > > > drm_dbg(&dev_priv->drm, > > > > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c > > > b/drivers/gpu/drm/i915/display/skl_universal_plane.c > > > > > index 28890876bdeb..e5cda5bcbde4 100644 > > > > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > > > > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > > > > > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier) > > > > > return PLANE_CTL_TILED_X; > > > > > case I915_FORMAT_MOD_Y_TILED: > > > > > return PLANE_CTL_TILED_Y; > > > > > + case I915_FORMAT_MOD_4_TILED: > > > > > + return PLANE_CTL_TILED_4; > > > > > case I915_FORMAT_MOD_Y_TILED_CCS: > > > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > > > > return PLANE_CTL_TILED_Y | > > > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; > > > > > @@ -1971,9 +1973,7 @@ static bool > > > gen12_plane_format_mod_supported(struct drm_plane *_plane, > > > > > case DRM_FORMAT_Y216: > > > > > case DRM_FORMAT_XVYU12_16161616: > > > > > case DRM_FORMAT_XVYU16161616: > > > > > - if (modifier == DRM_FORMAT_MOD_LINEAR || > > > > > - modifier == I915_FORMAT_MOD_X_TILED || > > > > > - modifier == I915_FORMAT_MOD_Y_TILED) > > > > > + if (!intel_fb_is_ccs_modifier(modifier)) > > > > > return true; > > > > > fallthrough; > > > > > default: > > > > > @@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct > intel_crtc > > > *crtc, > > > > > else > > > > > fb->modifier = I915_FORMAT_MOD_Y_TILED; > > > > > break; > > > > > - case PLANE_CTL_TILED_YF: > > > > > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) > > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; > > > > > - else > > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED; > > > > > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on > XE_LPD+ */ > > > > > > > > To be safe, maybe add a static_assert(PLANE_CTL_TILED_YF == > > > > PLANE_CTL_TILED_4); ? > > > > > > > > > + if (HAS_4TILE(dev_priv)) { > > > > > + fb->modifier = I915_FORMAT_MOD_4_TILED; > > > > > + } else { > > > > > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) > > > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; > > > > > + else > > > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED; > > > > > + } > > > > > break; > > > > > default: > > > > > MISSING_CASE(tiling); > > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h > > > b/drivers/gpu/drm/i915/i915_drv.h > > > > > index 1bfadd9127fc..3d90bd732e91 100644 > > > > > --- a/drivers/gpu/drm/i915/i915_drv.h > > > > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > > > > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct > drm_i915_private > > > *i915, > > > > > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) > == 7) > > > > > > > > > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) > > > > > +#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile) > > > > > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) > > > > > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) > > > > > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6) > > > > > diff --git a/drivers/gpu/drm/i915/i915_pci.c > > > b/drivers/gpu/drm/i915/i915_pci.c > > > > > index f01cba4ec283..403d3a581ce7 100644 > > > > > --- a/drivers/gpu/drm/i915/i915_pci.c > > > > > +++ b/drivers/gpu/drm/i915/i915_pci.c > > > > > @@ -1044,6 +1044,7 @@ static const struct intel_device_info dg2_info > = { > > > > > DGFX_FEATURES, > > > > > .graphics.rel = 55, > > > > > .media.rel = 55, > > > > > + .has_4tile = 1, > > > > > PLATFORM(INTEL_DG2), > > > > > .platform_engine_mask = > > > > > BIT(RCS0) | BIT(BCS0) | > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > > b/drivers/gpu/drm/i915/i915_reg.h > > > > > index 3450818802c2..22d18a292430 100644 > > > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > > > @@ -7284,6 +7284,7 @@ enum { > > > > > #define PLANE_CTL_TILED_X (1 << 10) > > > > > #define PLANE_CTL_TILED_Y (4 << 10) > > > > > #define PLANE_CTL_TILED_YF (5 << 10) > > > > > +#define PLANE_CTL_TILED_4 (5 << 10) > > > > > #define PLANE_CTL_ASYNC_FLIP (1 << 9) > > > > > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8) > > > > > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* > TGL+ */ > > > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h > > > b/drivers/gpu/drm/i915/intel_device_info.h > > > > > index 669f0d26c3c3..67177e18704a 100644 > > > > > --- a/drivers/gpu/drm/i915/intel_device_info.h > > > > > +++ b/drivers/gpu/drm/i915/intel_device_info.h > > > > > @@ -125,6 +125,7 @@ enum intel_ppgtt_type { > > > > > func(has_64bit_reloc); \ > > > > > func(gpu_reset_clobbers_display); \ > > > > > func(has_reset_engine); \ > > > > > + func(has_4tile); \ > > > > > func(has_global_mocs); \ > > > > > func(has_gt_uc); \ > > > > > func(has_l3_dpf); \ > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > > b/drivers/gpu/drm/i915/intel_pm.c > > > > > index 01fa3fac1b57..167704f0acf0 100644 > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > > > > @@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct > > > intel_crtc_state *crtc_state, > > > > > } > > > > > > > > > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED || > > > > > + modifier == I915_FORMAT_MOD_4_TILED || > > > > > modifier == I915_FORMAT_MOD_Yf_TILED || > > > > > modifier == I915_FORMAT_MOD_Y_TILED_CCS || > > > > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS; > > > > > diff --git a/include/uapi/drm/drm_fourcc.h > > > b/include/uapi/drm/drm_fourcc.h > > > > > index 7f652c96845b..41184a94935d 100644 > > > > > --- a/include/uapi/drm/drm_fourcc.h > > > > > +++ b/include/uapi/drm/drm_fourcc.h > > > > > @@ -564,6 +564,14 @@ extern "C" { > > > > > * pitch is required to be a multiple of 4 tile widths. > > > > > */ > > > > > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC > > > fourcc_mod_code(INTEL, 8) > > > > > +/* > > > > > + * Intel F-tiling(aka Tile4) layout > > > > > + * > > > > > > > > v4 and v5 attempted to get rid of the F-tile references, but this was > > > > left behind. > > > > > > > > > + * This is a tiled layout using 4Kb tiles in row-major layout. > > > > > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD > > > > > + * (16 bytes) chunks column-major.. > > > > > > > > I can't picture how tile 4 is organized from this description. Could > > > > we update it? > > > > Here's a draft I came up with when wondering how I might do this myself: > > > > > > > > * This is a tiled layout using 4KB tiles in a row-major layout. It has the same > > > > * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It > > > > * only differs from Tile Y at the 256B granularity in between. At this > > > > * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape > > > > * of 64B x 8 rows. > > > > > > > > -Nanley > > > > > > > > > + */ > > > > > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9) > > > > > > > > > > /* > > > > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks > > > > > -- > > > > > 2.24.1.485.gad05a3d8e5 > > > > >
On Tue, Nov 23, 2021 at 05:06:22PM +0200, Chery, Nanley G wrote: > > > > -----Original Message----- > > From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com> > > Sent: Tuesday, November 23, 2021 8:37 AM > > To: Chery, Nanley G <nanley.g.chery@intel.com> > > Cc: Nanley Chery <nanleychery@gmail.com>; intel-gfx@lists.freedesktop.org > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support > > > > On Tue, Nov 23, 2021 at 02:41:20PM +0200, Chery, Nanley G wrote: > > > > > > > > > > -----Original Message----- > > > > From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com> > > > > Sent: Tuesday, November 23, 2021 3:14 AM > > > > To: Nanley Chery <nanleychery@gmail.com> > > > > Cc: intel-gfx@lists.freedesktop.org; Chery, Nanley G > > > > <nanley.g.chery@intel.com> > > > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format > > > > support > > > > > > > > On Mon, Nov 22, 2021 at 05:08:31PM -0500, Nanley Chery wrote: > > > > > Hi Stanislav, > > > > > > > > > > Are there IGT tests for this modifier? > > > > > > > > Hi Nanley > > > > > > > > Yes, there should be plenty of those, not sure they are all sent to > > > > upstream though. > > > > We have a separate team doing this. > > > > That modifier should be added to kms_plane_multiple and many others > > > > > > > > > > Okay, I'll be on the lookout for them. > > > > > > > Stan > > > > > > > > > > Looks like you missed the other review comments I left in my prior email. > > > > Oh, sorry just saw those. I pushed this already, I will check those anyway > > and sent additional patch, if needed. > > > > Where has this been pushed to? We're still requiring an Ack from userspace/mesa to get new modifiers upstream, right? It was pushed to drm-intel-next. To be honest, I was not aware that this requires userspace/mesa ack. How do we proceed then? Should I revert and push the fixed version or do we wait until IGT part gets merged? Stan > > -Nanley > > > Stan > > > > > > > > -Nanley > > > > > > > > > > > > > On Mon, Nov 22, 2021 at 4:14 PM Stanislav Lisovskiy > > > > > <stanislav.lisovskiy@intel.com> wrote: > > > > > > > > > > > > TileF(Tile4 in bspec) format is 4K tile organized into > > > > > > 64B subtiles with same basic shape as for legacy TileY > > > > > > which will be supported by Display13. > > > > > > > > > > > > v2: - Fixed wrong case condition(Jani Nikula) > > > > > > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak) > > > > > > > > > > > > v3: - s/I915_TILING_F/TILING_4/g > > > > > > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g > > > > > > - Removed unneeded fencing code > > > > > > > > > > > > v4: - Rebased, fixed merge conflict with new table-oriented > > > > > > format modifier checking(Stan) > > > > > > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan) > > > > > > > > > > > > v5: - Still had to remove some Tile F mentionings > > > > > > - Moved has_4tile from adlp to DG2(Ramalingam C) > > > > > > - Check specifically for DG2, but not the Display13(Imre) > > > > > > > > > > > > v6: - Moved Tile4 assocating struct for modifier/display to > > > > > > the beginning(Imre Deak) > > > > > > - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier > > > > > > checks(Imre Deak) > > > > > > - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12 > > > > > > (Imre Deak) > > > > > > > > > > > > v7: - Fixed display_ver to { 13, 13 }(Imre Deak) > > > > > > - Removed redundant newline(Imre Deak) > > > > > > > > > > > > Reviewed-by: Imre Deak <imre.deak@intel.com> > > > > > > Cc: Imre Deak <imre.deak@intel.com> > > > > > > Cc: Matt Roper <matthew.d.roper@intel.com> > > > > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > > > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > > > > > > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com> > > > > > > --- > > > > > > drivers/gpu/drm/i915/display/intel_display.c | 1 + > > > > > > drivers/gpu/drm/i915/display/intel_fb.c | 9 +++++++++ > > > > > > drivers/gpu/drm/i915/display/intel_fbc.c | 1 + > > > > > > .../drm/i915/display/intel_plane_initial.c | 1 + > > > > > > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++-------- > > > > > > drivers/gpu/drm/i915/i915_drv.h | 1 + > > > > > > drivers/gpu/drm/i915/i915_pci.c | 1 + > > > > > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > > > > > drivers/gpu/drm/i915/intel_device_info.h | 1 + > > > > > > drivers/gpu/drm/i915/intel_pm.c | 1 + > > > > > > include/uapi/drm/drm_fourcc.h | 8 ++++++++ > > > > > > 11 files changed, 37 insertions(+), 8 deletions(-) > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > > > b/drivers/gpu/drm/i915/display/intel_display.c > > > > > > index f3c9208a30b1..7429965d3682 100644 > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > > > > @@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct > > > > intel_atomic_state *state, struct int > > > > > > case I915_FORMAT_MOD_X_TILED: > > > > > > case I915_FORMAT_MOD_Y_TILED: > > > > > > case I915_FORMAT_MOD_Yf_TILED: > > > > > > + case I915_FORMAT_MOD_4_TILED: > > > > > > break; > > > > > > default: > > > > > > drm_dbg_kms(&i915->drm, > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c > > > > b/drivers/gpu/drm/i915/display/intel_fb.c > > > > > > index c4a743d0913f..b7f1ef62072c 100644 > > > > > > --- a/drivers/gpu/drm/i915/display/intel_fb.c > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c > > > > > > @@ -139,6 +139,9 @@ struct intel_modifier_desc { > > > > > > > > > > > > static const struct intel_modifier_desc intel_modifiers[] = { > > > > > > { > > > > > > + .modifier = I915_FORMAT_MOD_4_TILED, > > > > > > + .display_ver = { 13, 13 }, > > > > > > > > > > I see that every other modifier has the plane_cap field set. Why is it > > > > > okay for it to be zero here? > > > > > > > > > > > + }, { > > > > > > .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, > > > > > > .display_ver = { 12, 13 }, > > > > > > .plane_caps = INTEL_PLANE_CAP_TILING_Y | > > > > INTEL_PLANE_CAP_CCS_MC, > > > > > > @@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct > > > > drm_framebuffer *fb, int color_plane) > > > > > > return 128; > > > > > > else > > > > > > return 512; > > > > > > + case I915_FORMAT_MOD_4_TILED: > > > > > > + /* > > > > > > + * Each 4K tile consists of 64B(8*8) subtiles, with > > > > > > + * same shape as Y Tile(i.e 4*16B OWords) > > > > > > + */ > > > > > > + return 128; > > > > > > case I915_FORMAT_MOD_Y_TILED_CCS: > > > > > > if (intel_fb_is_ccs_aux_plane(fb, color_plane)) > > > > > > return 128; > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c > > > > b/drivers/gpu/drm/i915/display/intel_fbc.c > > > > > > index d0c34bc3af6c..0ceabe40d8c9 100644 > > > > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > > > > > @@ -898,6 +898,7 @@ static bool tiling_is_valid(struct > > drm_i915_private > > > > *i915, > > > > > > case I915_FORMAT_MOD_Y_TILED: > > > > > > case I915_FORMAT_MOD_Yf_TILED: > > > > > > return DISPLAY_VER(i915) >= 9; > > > > > > + case I915_FORMAT_MOD_4_TILED: > > > > > > > > > > The tile Y cases above check the display version. Should we do the same > > here? > > > > > > > > > > > case I915_FORMAT_MOD_X_TILED: > > > > > > return true; > > > > > > default: > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c > > > > b/drivers/gpu/drm/i915/display/intel_plane_initial.c > > > > > > index dcd698a02da2..d80855ee9b96 100644 > > > > > > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c > > > > > > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc > > *crtc, > > > > > > case DRM_FORMAT_MOD_LINEAR: > > > > > > case I915_FORMAT_MOD_X_TILED: > > > > > > case I915_FORMAT_MOD_Y_TILED: > > > > > > + case I915_FORMAT_MOD_4_TILED: > > > > > > break; > > > > > > default: > > > > > > drm_dbg(&dev_priv->drm, > > > > > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c > > > > b/drivers/gpu/drm/i915/display/skl_universal_plane.c > > > > > > index 28890876bdeb..e5cda5bcbde4 100644 > > > > > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > > > > > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > > > > > > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier) > > > > > > return PLANE_CTL_TILED_X; > > > > > > case I915_FORMAT_MOD_Y_TILED: > > > > > > return PLANE_CTL_TILED_Y; > > > > > > + case I915_FORMAT_MOD_4_TILED: > > > > > > + return PLANE_CTL_TILED_4; > > > > > > case I915_FORMAT_MOD_Y_TILED_CCS: > > > > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > > > > > return PLANE_CTL_TILED_Y | > > > > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; > > > > > > @@ -1971,9 +1973,7 @@ static bool > > > > gen12_plane_format_mod_supported(struct drm_plane *_plane, > > > > > > case DRM_FORMAT_Y216: > > > > > > case DRM_FORMAT_XVYU12_16161616: > > > > > > case DRM_FORMAT_XVYU16161616: > > > > > > - if (modifier == DRM_FORMAT_MOD_LINEAR || > > > > > > - modifier == I915_FORMAT_MOD_X_TILED || > > > > > > - modifier == I915_FORMAT_MOD_Y_TILED) > > > > > > + if (!intel_fb_is_ccs_modifier(modifier)) > > > > > > return true; > > > > > > fallthrough; > > > > > > default: > > > > > > @@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct > > intel_crtc > > > > *crtc, > > > > > > else > > > > > > fb->modifier = I915_FORMAT_MOD_Y_TILED; > > > > > > break; > > > > > > - case PLANE_CTL_TILED_YF: > > > > > > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) > > > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; > > > > > > - else > > > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED; > > > > > > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on > > XE_LPD+ */ > > > > > > > > > > To be safe, maybe add a static_assert(PLANE_CTL_TILED_YF == > > > > > PLANE_CTL_TILED_4); ? > > > > > > > > > > > + if (HAS_4TILE(dev_priv)) { > > > > > > + fb->modifier = I915_FORMAT_MOD_4_TILED; > > > > > > + } else { > > > > > > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) > > > > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; > > > > > > + else > > > > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED; > > > > > > + } > > > > > > break; > > > > > > default: > > > > > > MISSING_CASE(tiling); > > > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h > > > > b/drivers/gpu/drm/i915/i915_drv.h > > > > > > index 1bfadd9127fc..3d90bd732e91 100644 > > > > > > --- a/drivers/gpu/drm/i915/i915_drv.h > > > > > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > > > > > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct > > drm_i915_private > > > > *i915, > > > > > > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) > > == 7) > > > > > > > > > > > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) > > > > > > +#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile) > > > > > > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) > > > > > > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) > > > > > > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_pci.c > > > > b/drivers/gpu/drm/i915/i915_pci.c > > > > > > index f01cba4ec283..403d3a581ce7 100644 > > > > > > --- a/drivers/gpu/drm/i915/i915_pci.c > > > > > > +++ b/drivers/gpu/drm/i915/i915_pci.c > > > > > > @@ -1044,6 +1044,7 @@ static const struct intel_device_info dg2_info > > = { > > > > > > DGFX_FEATURES, > > > > > > .graphics.rel = 55, > > > > > > .media.rel = 55, > > > > > > + .has_4tile = 1, > > > > > > PLATFORM(INTEL_DG2), > > > > > > .platform_engine_mask = > > > > > > BIT(RCS0) | BIT(BCS0) | > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > > > b/drivers/gpu/drm/i915/i915_reg.h > > > > > > index 3450818802c2..22d18a292430 100644 > > > > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > > > > @@ -7284,6 +7284,7 @@ enum { > > > > > > #define PLANE_CTL_TILED_X (1 << 10) > > > > > > #define PLANE_CTL_TILED_Y (4 << 10) > > > > > > #define PLANE_CTL_TILED_YF (5 << 10) > > > > > > +#define PLANE_CTL_TILED_4 (5 << 10) > > > > > > #define PLANE_CTL_ASYNC_FLIP (1 << 9) > > > > > > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8) > > > > > > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* > > TGL+ */ > > > > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h > > > > b/drivers/gpu/drm/i915/intel_device_info.h > > > > > > index 669f0d26c3c3..67177e18704a 100644 > > > > > > --- a/drivers/gpu/drm/i915/intel_device_info.h > > > > > > +++ b/drivers/gpu/drm/i915/intel_device_info.h > > > > > > @@ -125,6 +125,7 @@ enum intel_ppgtt_type { > > > > > > func(has_64bit_reloc); \ > > > > > > func(gpu_reset_clobbers_display); \ > > > > > > func(has_reset_engine); \ > > > > > > + func(has_4tile); \ > > > > > > func(has_global_mocs); \ > > > > > > func(has_gt_uc); \ > > > > > > func(has_l3_dpf); \ > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > > > b/drivers/gpu/drm/i915/intel_pm.c > > > > > > index 01fa3fac1b57..167704f0acf0 100644 > > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c > > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > > > > > @@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct > > > > intel_crtc_state *crtc_state, > > > > > > } > > > > > > > > > > > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED || > > > > > > + modifier == I915_FORMAT_MOD_4_TILED || > > > > > > modifier == I915_FORMAT_MOD_Yf_TILED || > > > > > > modifier == I915_FORMAT_MOD_Y_TILED_CCS || > > > > > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS; > > > > > > diff --git a/include/uapi/drm/drm_fourcc.h > > > > b/include/uapi/drm/drm_fourcc.h > > > > > > index 7f652c96845b..41184a94935d 100644 > > > > > > --- a/include/uapi/drm/drm_fourcc.h > > > > > > +++ b/include/uapi/drm/drm_fourcc.h > > > > > > @@ -564,6 +564,14 @@ extern "C" { > > > > > > * pitch is required to be a multiple of 4 tile widths. > > > > > > */ > > > > > > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC > > > > fourcc_mod_code(INTEL, 8) > > > > > > +/* > > > > > > + * Intel F-tiling(aka Tile4) layout > > > > > > + * > > > > > > > > > > v4 and v5 attempted to get rid of the F-tile references, but this was > > > > > left behind. > > > > > > > > > > > + * This is a tiled layout using 4Kb tiles in row-major layout. > > > > > > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD > > > > > > + * (16 bytes) chunks column-major.. > > > > > > > > > > I can't picture how tile 4 is organized from this description. Could > > > > > we update it? > > > > > Here's a draft I came up with when wondering how I might do this myself: > > > > > > > > > > * This is a tiled layout using 4KB tiles in a row-major layout. It has the same > > > > > * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It > > > > > * only differs from Tile Y at the 256B granularity in between. At this > > > > > * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape > > > > > * of 64B x 8 rows. > > > > > > > > > > -Nanley > > > > > > > > > > > + */ > > > > > > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9) > > > > > > > > > > > > /* > > > > > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks > > > > > > -- > > > > > > 2.24.1.485.gad05a3d8e5 > > > > > >
> -----Original Message----- > From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com> > Sent: Tuesday, November 23, 2021 10:23 AM > To: Chery, Nanley G <nanley.g.chery@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Deak, Imre <imre.deak@intel.com> > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support > > On Tue, Nov 23, 2021 at 05:06:22PM +0200, Chery, Nanley G wrote: > > > > > > > -----Original Message----- > > > From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com> > > > Sent: Tuesday, November 23, 2021 8:37 AM > > > To: Chery, Nanley G <nanley.g.chery@intel.com> > > > Cc: Nanley Chery <nanleychery@gmail.com>; > > > intel-gfx@lists.freedesktop.org > > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format > > > support > > > > > > On Tue, Nov 23, 2021 at 02:41:20PM +0200, Chery, Nanley G wrote: > > > > > > > > > > > > > -----Original Message----- > > > > > From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com> > > > > > Sent: Tuesday, November 23, 2021 3:14 AM > > > > > To: Nanley Chery <nanleychery@gmail.com> > > > > > Cc: intel-gfx@lists.freedesktop.org; Chery, Nanley G > > > > > <nanley.g.chery@intel.com> > > > > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane > > > > > format support > > > > > > > > > > On Mon, Nov 22, 2021 at 05:08:31PM -0500, Nanley Chery wrote: > > > > > > Hi Stanislav, > > > > > > > > > > > > Are there IGT tests for this modifier? > > > > > > > > > > Hi Nanley > > > > > > > > > > Yes, there should be plenty of those, not sure they are all sent > > > > > to upstream though. > > > > > We have a separate team doing this. > > > > > That modifier should be added to kms_plane_multiple and many > > > > > others > > > > > > > > > > > > > Okay, I'll be on the lookout for them. > > > > > > > > > Stan > > > > > > > > > > > > > Looks like you missed the other review comments I left in my prior email. > > > > > > Oh, sorry just saw those. I pushed this already, I will check those > > > anyway and sent additional patch, if needed. > > > > > > > Where has this been pushed to? We're still requiring an Ack from > userspace/mesa to get new modifiers upstream, right? > > It was pushed to drm-intel-next. To be honest, I was not aware that this requires > userspace/mesa ack. > Yeah, I don't think much of the process has been documented. Might be good for us to discuss and/or put something together. The ack was something we did in the last cycle and it seemed like something we were going to do for this one as well. > How do we proceed then? Should I revert and push the fixed version or do we > wait until IGT part gets merged? > Reverting and waiting for IGT tests to at least be on the list seems like a reasonable plan to me. I also think it's a good idea to continue waiting on an ack from mesa as well. I'll be OOO this week for holidays, but I'm happy to discuss the latter bit when I get back. -Nanley > Stan > > > > > -Nanley > > > > > Stan > > > > > > > > > > > -Nanley > > > > > > > > > > > > > > > > On Mon, Nov 22, 2021 at 4:14 PM Stanislav Lisovskiy > > > > > > <stanislav.lisovskiy@intel.com> wrote: > > > > > > > > > > > > > > TileF(Tile4 in bspec) format is 4K tile organized into 64B > > > > > > > subtiles with same basic shape as for legacy TileY which > > > > > > > will be supported by Display13. > > > > > > > > > > > > > > v2: - Fixed wrong case condition(Jani Nikula) > > > > > > > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak) > > > > > > > > > > > > > > v3: - s/I915_TILING_F/TILING_4/g > > > > > > > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g > > > > > > > - Removed unneeded fencing code > > > > > > > > > > > > > > v4: - Rebased, fixed merge conflict with new table-oriented > > > > > > > format modifier checking(Stan) > > > > > > > - Replaced the rest of "Tile F" mentions to "Tile > > > > > > > 4"(Stan) > > > > > > > > > > > > > > v5: - Still had to remove some Tile F mentionings > > > > > > > - Moved has_4tile from adlp to DG2(Ramalingam C) > > > > > > > - Check specifically for DG2, but not the > > > > > > > Display13(Imre) > > > > > > > > > > > > > > v6: - Moved Tile4 assocating struct for modifier/display to > > > > > > > the beginning(Imre Deak) > > > > > > > - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier > > > > > > > checks(Imre Deak) > > > > > > > - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12 > > > > > > > (Imre Deak) > > > > > > > > > > > > > > v7: - Fixed display_ver to { 13, 13 }(Imre Deak) > > > > > > > - Removed redundant newline(Imre Deak) > > > > > > > > > > > > > > Reviewed-by: Imre Deak <imre.deak@intel.com> > > > > > > > Cc: Imre Deak <imre.deak@intel.com> > > > > > > > Cc: Matt Roper <matthew.d.roper@intel.com> > > > > > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > > > > > > > Signed-off-by: Stanislav Lisovskiy > > > > > > > <stanislav.lisovskiy@intel.com> > > > > > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > > > > > > > Signed-off-by: Juha-Pekka Heikkilä > > > > > > > <juha-pekka.heikkila@intel.com> > > > > > > > --- > > > > > > > drivers/gpu/drm/i915/display/intel_display.c | 1 + > > > > > > > drivers/gpu/drm/i915/display/intel_fb.c | 9 +++++++++ > > > > > > > drivers/gpu/drm/i915/display/intel_fbc.c | 1 + > > > > > > > .../drm/i915/display/intel_plane_initial.c | 1 + > > > > > > > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++-------- > > > > > > > drivers/gpu/drm/i915/i915_drv.h | 1 + > > > > > > > drivers/gpu/drm/i915/i915_pci.c | 1 + > > > > > > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > > > > > > drivers/gpu/drm/i915/intel_device_info.h | 1 + > > > > > > > drivers/gpu/drm/i915/intel_pm.c | 1 + > > > > > > > include/uapi/drm/drm_fourcc.h | 8 ++++++++ > > > > > > > 11 files changed, 37 insertions(+), 8 deletions(-) > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > > > > b/drivers/gpu/drm/i915/display/intel_display.c > > > > > > > index f3c9208a30b1..7429965d3682 100644 > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > > > > > @@ -7766,6 +7766,7 @@ static int > > > > > > > intel_atomic_check_async(struct > > > > > intel_atomic_state *state, struct int > > > > > > > case I915_FORMAT_MOD_X_TILED: > > > > > > > case I915_FORMAT_MOD_Y_TILED: > > > > > > > case I915_FORMAT_MOD_Yf_TILED: > > > > > > > + case I915_FORMAT_MOD_4_TILED: > > > > > > > break; > > > > > > > default: > > > > > > > drm_dbg_kms(&i915->drm, diff --git > > > > > > > a/drivers/gpu/drm/i915/display/intel_fb.c > > > > > b/drivers/gpu/drm/i915/display/intel_fb.c > > > > > > > index c4a743d0913f..b7f1ef62072c 100644 > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_fb.c > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c > > > > > > > @@ -139,6 +139,9 @@ struct intel_modifier_desc { > > > > > > > > > > > > > > static const struct intel_modifier_desc intel_modifiers[] = { > > > > > > > { > > > > > > > + .modifier = I915_FORMAT_MOD_4_TILED, > > > > > > > + .display_ver = { 13, 13 }, > > > > > > > > > > > > I see that every other modifier has the plane_cap field set. > > > > > > Why is it okay for it to be zero here? > > > > > > > > > > > > > + }, { > > > > > > > .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, > > > > > > > .display_ver = { 12, 13 }, > > > > > > > .plane_caps = INTEL_PLANE_CAP_TILING_Y | > > > > > INTEL_PLANE_CAP_CCS_MC, > > > > > > > @@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct > > > > > drm_framebuffer *fb, int color_plane) > > > > > > > return 128; > > > > > > > else > > > > > > > return 512; > > > > > > > + case I915_FORMAT_MOD_4_TILED: > > > > > > > + /* > > > > > > > + * Each 4K tile consists of 64B(8*8) subtiles, with > > > > > > > + * same shape as Y Tile(i.e 4*16B OWords) > > > > > > > + */ > > > > > > > + return 128; > > > > > > > case I915_FORMAT_MOD_Y_TILED_CCS: > > > > > > > if (intel_fb_is_ccs_aux_plane(fb, color_plane)) > > > > > > > return 128; diff --git > > > > > > > a/drivers/gpu/drm/i915/display/intel_fbc.c > > > > > b/drivers/gpu/drm/i915/display/intel_fbc.c > > > > > > > index d0c34bc3af6c..0ceabe40d8c9 100644 > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > > > > > > @@ -898,6 +898,7 @@ static bool tiling_is_valid(struct > > > drm_i915_private > > > > > *i915, > > > > > > > case I915_FORMAT_MOD_Y_TILED: > > > > > > > case I915_FORMAT_MOD_Yf_TILED: > > > > > > > return DISPLAY_VER(i915) >= 9; > > > > > > > + case I915_FORMAT_MOD_4_TILED: > > > > > > > > > > > > The tile Y cases above check the display version. Should we do > > > > > > the same > > > here? > > > > > > > > > > > > > case I915_FORMAT_MOD_X_TILED: > > > > > > > return true; > > > > > > > default: > > > > > > > diff --git > > > > > > > a/drivers/gpu/drm/i915/display/intel_plane_initial.c > > > > > b/drivers/gpu/drm/i915/display/intel_plane_initial.c > > > > > > > index dcd698a02da2..d80855ee9b96 100644 > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c > > > > > > > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct > > > > > > > intel_crtc > > > *crtc, > > > > > > > case DRM_FORMAT_MOD_LINEAR: > > > > > > > case I915_FORMAT_MOD_X_TILED: > > > > > > > case I915_FORMAT_MOD_Y_TILED: > > > > > > > + case I915_FORMAT_MOD_4_TILED: > > > > > > > break; > > > > > > > default: > > > > > > > drm_dbg(&dev_priv->drm, diff --git > > > > > > > a/drivers/gpu/drm/i915/display/skl_universal_plane.c > > > > > b/drivers/gpu/drm/i915/display/skl_universal_plane.c > > > > > > > index 28890876bdeb..e5cda5bcbde4 100644 > > > > > > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > > > > > > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > > > > > > > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 > fb_modifier) > > > > > > > return PLANE_CTL_TILED_X; > > > > > > > case I915_FORMAT_MOD_Y_TILED: > > > > > > > return PLANE_CTL_TILED_Y; > > > > > > > + case I915_FORMAT_MOD_4_TILED: > > > > > > > + return PLANE_CTL_TILED_4; > > > > > > > case I915_FORMAT_MOD_Y_TILED_CCS: > > > > > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > > > > > > return PLANE_CTL_TILED_Y | > > > > > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; > > > > > > > @@ -1971,9 +1973,7 @@ static bool > > > > > gen12_plane_format_mod_supported(struct drm_plane *_plane, > > > > > > > case DRM_FORMAT_Y216: > > > > > > > case DRM_FORMAT_XVYU12_16161616: > > > > > > > case DRM_FORMAT_XVYU16161616: > > > > > > > - if (modifier == DRM_FORMAT_MOD_LINEAR || > > > > > > > - modifier == I915_FORMAT_MOD_X_TILED || > > > > > > > - modifier == I915_FORMAT_MOD_Y_TILED) > > > > > > > + if (!intel_fb_is_ccs_modifier(modifier)) > > > > > > > return true; > > > > > > > fallthrough; > > > > > > > default: > > > > > > > @@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct > > > intel_crtc > > > > > *crtc, > > > > > > > else > > > > > > > fb->modifier = I915_FORMAT_MOD_Y_TILED; > > > > > > > break; > > > > > > > - case PLANE_CTL_TILED_YF: > > > > > > > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) > > > > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; > > > > > > > - else > > > > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED; > > > > > > > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on > > > XE_LPD+ */ > > > > > > > > > > > > To be safe, maybe add a static_assert(PLANE_CTL_TILED_YF == > > > > > > PLANE_CTL_TILED_4); ? > > > > > > > > > > > > > + if (HAS_4TILE(dev_priv)) { > > > > > > > + fb->modifier = I915_FORMAT_MOD_4_TILED; > > > > > > > + } else { > > > > > > > + if (val & > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) > > > > > > > + fb->modifier = > I915_FORMAT_MOD_Yf_TILED_CCS; > > > > > > > + else > > > > > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED; > > > > > > > + } > > > > > > > break; > > > > > > > default: > > > > > > > MISSING_CASE(tiling); diff --git > > > > > > > a/drivers/gpu/drm/i915/i915_drv.h > > > > > b/drivers/gpu/drm/i915/i915_drv.h > > > > > > > index 1bfadd9127fc..3d90bd732e91 100644 > > > > > > > --- a/drivers/gpu/drm/i915/i915_drv.h > > > > > > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > > > > > > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct > > > drm_i915_private > > > > > *i915, > > > > > > > #define CMDPARSER_USES_GGTT(dev_priv) > > > > > > > (GRAPHICS_VER(dev_priv) > > > == 7) > > > > > > > > > > > > > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) > > > > > > > +#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile) > > > > > > > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) > > > > > > > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) > > > > > > > #define HAS_SECURE_BATCHES(dev_priv) > > > > > > > (GRAPHICS_VER(dev_priv) < 6) diff --git > > > > > > > a/drivers/gpu/drm/i915/i915_pci.c > > > > > b/drivers/gpu/drm/i915/i915_pci.c > > > > > > > index f01cba4ec283..403d3a581ce7 100644 > > > > > > > --- a/drivers/gpu/drm/i915/i915_pci.c > > > > > > > +++ b/drivers/gpu/drm/i915/i915_pci.c > > > > > > > @@ -1044,6 +1044,7 @@ static const struct intel_device_info > > > > > > > dg2_info > > > = { > > > > > > > DGFX_FEATURES, > > > > > > > .graphics.rel = 55, > > > > > > > .media.rel = 55, > > > > > > > + .has_4tile = 1, > > > > > > > PLATFORM(INTEL_DG2), > > > > > > > .platform_engine_mask = > > > > > > > BIT(RCS0) | BIT(BCS0) | diff --git > > > > > > > a/drivers/gpu/drm/i915/i915_reg.h > > > > > b/drivers/gpu/drm/i915/i915_reg.h > > > > > > > index 3450818802c2..22d18a292430 100644 > > > > > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > > > > > @@ -7284,6 +7284,7 @@ enum { > > > > > > > #define PLANE_CTL_TILED_X (1 << 10) > > > > > > > #define PLANE_CTL_TILED_Y (4 << 10) > > > > > > > #define PLANE_CTL_TILED_YF (5 << 10) > > > > > > > +#define PLANE_CTL_TILED_4 (5 << 10) > > > > > > > #define PLANE_CTL_ASYNC_FLIP (1 << 9) > > > > > > > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8) > > > > > > > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* > > > TGL+ */ > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h > > > > > b/drivers/gpu/drm/i915/intel_device_info.h > > > > > > > index 669f0d26c3c3..67177e18704a 100644 > > > > > > > --- a/drivers/gpu/drm/i915/intel_device_info.h > > > > > > > +++ b/drivers/gpu/drm/i915/intel_device_info.h > > > > > > > @@ -125,6 +125,7 @@ enum intel_ppgtt_type { > > > > > > > func(has_64bit_reloc); \ > > > > > > > func(gpu_reset_clobbers_display); \ > > > > > > > func(has_reset_engine); \ > > > > > > > + func(has_4tile); \ > > > > > > > func(has_global_mocs); \ > > > > > > > func(has_gt_uc); \ > > > > > > > func(has_l3_dpf); \ > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > > > > b/drivers/gpu/drm/i915/intel_pm.c > > > > > > > index 01fa3fac1b57..167704f0acf0 100644 > > > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c > > > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > > > > > > @@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct > > > > > intel_crtc_state *crtc_state, > > > > > > > } > > > > > > > > > > > > > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED || > > > > > > > + modifier == I915_FORMAT_MOD_4_TILED || > > > > > > > modifier == I915_FORMAT_MOD_Yf_TILED || > > > > > > > modifier == I915_FORMAT_MOD_Y_TILED_CCS || > > > > > > > modifier == > > > > > > > I915_FORMAT_MOD_Yf_TILED_CCS; diff --git > > > > > > > a/include/uapi/drm/drm_fourcc.h > > > > > b/include/uapi/drm/drm_fourcc.h > > > > > > > index 7f652c96845b..41184a94935d 100644 > > > > > > > --- a/include/uapi/drm/drm_fourcc.h > > > > > > > +++ b/include/uapi/drm/drm_fourcc.h > > > > > > > @@ -564,6 +564,14 @@ extern "C" { > > > > > > > * pitch is required to be a multiple of 4 tile widths. > > > > > > > */ > > > > > > > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC > > > > > fourcc_mod_code(INTEL, 8) > > > > > > > +/* > > > > > > > + * Intel F-tiling(aka Tile4) layout > > > > > > > + * > > > > > > > > > > > > v4 and v5 attempted to get rid of the F-tile references, but > > > > > > this was left behind. > > > > > > > > > > > > > + * This is a tiled layout using 4Kb tiles in row-major layout. > > > > > > > + * Within the tile pixels are laid out in 64 byte units / > > > > > > > + sub-tiles in OWORD > > > > > > > + * (16 bytes) chunks column-major.. > > > > > > > > > > > > I can't picture how tile 4 is organized from this description. > > > > > > Could we update it? > > > > > > Here's a draft I came up with when wondering how I might do this > myself: > > > > > > > > > > > > * This is a tiled layout using 4KB tiles in a row-major > > > > > > layout. It has the same > > > > > > * shape as Tile Y at two granularities: 4KB (128B x 32) and > > > > > > 64B (16B x 4). It > > > > > > * only differs from Tile Y at the 256B granularity in between. > > > > > > At this > > > > > > * granularity, Tile Y has a shape of 16B x 32 rows, but this > > > > > > tiling has a shape > > > > > > * of 64B x 8 rows. > > > > > > > > > > > > -Nanley > > > > > > > > > > > > > + */ > > > > > > > +#define I915_FORMAT_MOD_4_TILED > fourcc_mod_code(INTEL, 9) > > > > > > > > > > > > > > /* > > > > > > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) > > > > > > > -sized macroblocks > > > > > > > -- > > > > > > > 2.24.1.485.gad05a3d8e5 > > > > > > >
On Mon, Nov 22, 2021 at 05:08:31PM -0500, Nanley Chery wrote: > Hi Stanislav, > > Are there IGT tests for this modifier? > > On Mon, Nov 22, 2021 at 4:14 PM Stanislav Lisovskiy > <stanislav.lisovskiy@intel.com> wrote: > > > > TileF(Tile4 in bspec) format is 4K tile organized into > > 64B subtiles with same basic shape as for legacy TileY > > which will be supported by Display13. > > > > v2: - Fixed wrong case condition(Jani Nikula) > > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak) > > > > v3: - s/I915_TILING_F/TILING_4/g > > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g > > - Removed unneeded fencing code > > > > v4: - Rebased, fixed merge conflict with new table-oriented > > format modifier checking(Stan) > > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan) > > > > v5: - Still had to remove some Tile F mentionings > > - Moved has_4tile from adlp to DG2(Ramalingam C) > > - Check specifically for DG2, but not the Display13(Imre) > > > > v6: - Moved Tile4 assocating struct for modifier/display to > > the beginning(Imre Deak) > > - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier > > checks(Imre Deak) > > - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12 > > (Imre Deak) > > > > v7: - Fixed display_ver to { 13, 13 }(Imre Deak) > > - Removed redundant newline(Imre Deak) > > > > Reviewed-by: Imre Deak <imre.deak@intel.com> > > Cc: Imre Deak <imre.deak@intel.com> > > Cc: Matt Roper <matthew.d.roper@intel.com> > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 1 + > > drivers/gpu/drm/i915/display/intel_fb.c | 9 +++++++++ > > drivers/gpu/drm/i915/display/intel_fbc.c | 1 + > > .../drm/i915/display/intel_plane_initial.c | 1 + > > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++-------- > > drivers/gpu/drm/i915/i915_drv.h | 1 + > > drivers/gpu/drm/i915/i915_pci.c | 1 + > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > drivers/gpu/drm/i915/intel_device_info.h | 1 + > > drivers/gpu/drm/i915/intel_pm.c | 1 + > > include/uapi/drm/drm_fourcc.h | 8 ++++++++ > > 11 files changed, 37 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index f3c9208a30b1..7429965d3682 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int > > case I915_FORMAT_MOD_X_TILED: > > case I915_FORMAT_MOD_Y_TILED: > > case I915_FORMAT_MOD_Yf_TILED: > > + case I915_FORMAT_MOD_4_TILED: > > break; > > default: > > drm_dbg_kms(&i915->drm, > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c > > index c4a743d0913f..b7f1ef62072c 100644 > > --- a/drivers/gpu/drm/i915/display/intel_fb.c > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c > > @@ -139,6 +139,9 @@ struct intel_modifier_desc { > > > > static const struct intel_modifier_desc intel_modifiers[] = { > > { > > + .modifier = I915_FORMAT_MOD_4_TILED, > > + .display_ver = { 13, 13 }, > > I see that every other modifier has the plane_cap field set. Why is it > okay for it to be zero here? Yes, missed this. The INTEL_PLANE_CAP_TILING_4 flag needs to be added and returned from skl_get_plane_caps() for HAS_4TILE() platforms and here we need to set this flag. > > + }, { > > .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, > > .display_ver = { 12, 13 }, > > .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC, > > @@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) > > return 128; > > else > > return 512; > > + case I915_FORMAT_MOD_4_TILED: > > + /* > > + * Each 4K tile consists of 64B(8*8) subtiles, with > > + * same shape as Y Tile(i.e 4*16B OWords) > > + */ > > + return 128; > > case I915_FORMAT_MOD_Y_TILED_CCS: > > if (intel_fb_is_ccs_aux_plane(fb, color_plane)) > > return 128; > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > > index d0c34bc3af6c..0ceabe40d8c9 100644 > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > @@ -898,6 +898,7 @@ static bool tiling_is_valid(struct drm_i915_private *i915, > > case I915_FORMAT_MOD_Y_TILED: > > case I915_FORMAT_MOD_Yf_TILED: > > return DISPLAY_VER(i915) >= 9; > > + case I915_FORMAT_MOD_4_TILED: > > The tile Y cases above check the display version. Should we do the same here? I don't think we need a display version check (here or above), since the modifiers will be passed to this func only on platforms supporting them. > > case I915_FORMAT_MOD_X_TILED: > > return true; > > default: > > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c > > index dcd698a02da2..d80855ee9b96 100644 > > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c > > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c > > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc, > > case DRM_FORMAT_MOD_LINEAR: > > case I915_FORMAT_MOD_X_TILED: > > case I915_FORMAT_MOD_Y_TILED: > > + case I915_FORMAT_MOD_4_TILED: > > break; > > default: > > drm_dbg(&dev_priv->drm, > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c > > index 28890876bdeb..e5cda5bcbde4 100644 > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier) > > return PLANE_CTL_TILED_X; > > case I915_FORMAT_MOD_Y_TILED: > > return PLANE_CTL_TILED_Y; > > + case I915_FORMAT_MOD_4_TILED: > > + return PLANE_CTL_TILED_4; > > case I915_FORMAT_MOD_Y_TILED_CCS: > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; > > @@ -1971,9 +1973,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, > > case DRM_FORMAT_Y216: > > case DRM_FORMAT_XVYU12_16161616: > > case DRM_FORMAT_XVYU16161616: > > - if (modifier == DRM_FORMAT_MOD_LINEAR || > > - modifier == I915_FORMAT_MOD_X_TILED || > > - modifier == I915_FORMAT_MOD_Y_TILED) > > + if (!intel_fb_is_ccs_modifier(modifier)) > > return true; > > fallthrough; > > default: > > @@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, > > else > > fb->modifier = I915_FORMAT_MOD_Y_TILED; > > break; > > - case PLANE_CTL_TILED_YF: > > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; > > - else > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED; > > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */ > > To be safe, maybe add a static_assert(PLANE_CTL_TILED_YF == > PLANE_CTL_TILED_4); ? > > > + if (HAS_4TILE(dev_priv)) { > > + fb->modifier = I915_FORMAT_MOD_4_TILED; > > + } else { > > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; > > + else > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED; > > + } > > break; > > default: > > MISSING_CASE(tiling); > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > index 1bfadd9127fc..3d90bd732e91 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7) > > > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) > > +#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile) > > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) > > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) > > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6) > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > > index f01cba4ec283..403d3a581ce7 100644 > > --- a/drivers/gpu/drm/i915/i915_pci.c > > +++ b/drivers/gpu/drm/i915/i915_pci.c > > @@ -1044,6 +1044,7 @@ static const struct intel_device_info dg2_info = { > > DGFX_FEATURES, > > .graphics.rel = 55, > > .media.rel = 55, > > + .has_4tile = 1, > > PLATFORM(INTEL_DG2), > > .platform_engine_mask = > > BIT(RCS0) | BIT(BCS0) | > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 3450818802c2..22d18a292430 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -7284,6 +7284,7 @@ enum { > > #define PLANE_CTL_TILED_X (1 << 10) > > #define PLANE_CTL_TILED_Y (4 << 10) > > #define PLANE_CTL_TILED_YF (5 << 10) > > +#define PLANE_CTL_TILED_4 (5 << 10) > > #define PLANE_CTL_ASYNC_FLIP (1 << 9) > > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8) > > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */ > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > > index 669f0d26c3c3..67177e18704a 100644 > > --- a/drivers/gpu/drm/i915/intel_device_info.h > > +++ b/drivers/gpu/drm/i915/intel_device_info.h > > @@ -125,6 +125,7 @@ enum intel_ppgtt_type { > > func(has_64bit_reloc); \ > > func(gpu_reset_clobbers_display); \ > > func(has_reset_engine); \ > > + func(has_4tile); \ > > func(has_global_mocs); \ > > func(has_gt_uc); \ > > func(has_l3_dpf); \ > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index 01fa3fac1b57..167704f0acf0 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state, > > } > > > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED || > > + modifier == I915_FORMAT_MOD_4_TILED || > > modifier == I915_FORMAT_MOD_Yf_TILED || > > modifier == I915_FORMAT_MOD_Y_TILED_CCS || > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS; > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h > > index 7f652c96845b..41184a94935d 100644 > > --- a/include/uapi/drm/drm_fourcc.h > > +++ b/include/uapi/drm/drm_fourcc.h > > @@ -564,6 +564,14 @@ extern "C" { > > * pitch is required to be a multiple of 4 tile widths. > > */ > > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) > > +/* > > + * Intel F-tiling(aka Tile4) layout > > + * > > v4 and v5 attempted to get rid of the F-tile references, but this was > left behind. > > > + * This is a tiled layout using 4Kb tiles in row-major layout. > > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD > > + * (16 bytes) chunks column-major.. > > I can't picture how tile 4 is organized from this description. Could > we update it? > Here's a draft I came up with when wondering how I might do this myself: > > * This is a tiled layout using 4KB tiles in a row-major layout. It has the same > * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It > * only differs from Tile Y at the 256B granularity in between. At this > * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape > * of 64B x 8 rows. > > -Nanley > > > + */ > > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9) > > > > /* > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks > > -- > > 2.24.1.485.gad05a3d8e5 > >
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f3c9208a30b1..7429965d3682 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int case I915_FORMAT_MOD_X_TILED: case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Yf_TILED: + case I915_FORMAT_MOD_4_TILED: break; default: drm_dbg_kms(&i915->drm, diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index c4a743d0913f..b7f1ef62072c 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -139,6 +139,9 @@ struct intel_modifier_desc { static const struct intel_modifier_desc intel_modifiers[] = { { + .modifier = I915_FORMAT_MOD_4_TILED, + .display_ver = { 13, 13 }, + }, { .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, .display_ver = { 12, 13 }, .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC, @@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) return 128; else return 512; + case I915_FORMAT_MOD_4_TILED: + /* + * Each 4K tile consists of 64B(8*8) subtiles, with + * same shape as Y Tile(i.e 4*16B OWords) + */ + return 128; case I915_FORMAT_MOD_Y_TILED_CCS: if (intel_fb_is_ccs_aux_plane(fb, color_plane)) return 128; diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index d0c34bc3af6c..0ceabe40d8c9 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -898,6 +898,7 @@ static bool tiling_is_valid(struct drm_i915_private *i915, case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Yf_TILED: return DISPLAY_VER(i915) >= 9; + case I915_FORMAT_MOD_4_TILED: case I915_FORMAT_MOD_X_TILED: return true; default: diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c index dcd698a02da2..d80855ee9b96 100644 --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc, case DRM_FORMAT_MOD_LINEAR: case I915_FORMAT_MOD_X_TILED: case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_4_TILED: break; default: drm_dbg(&dev_priv->drm, diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 28890876bdeb..e5cda5bcbde4 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier) return PLANE_CTL_TILED_X; case I915_FORMAT_MOD_Y_TILED: return PLANE_CTL_TILED_Y; + case I915_FORMAT_MOD_4_TILED: + return PLANE_CTL_TILED_4; case I915_FORMAT_MOD_Y_TILED_CCS: case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; @@ -1971,9 +1973,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, case DRM_FORMAT_Y216: case DRM_FORMAT_XVYU12_16161616: case DRM_FORMAT_XVYU16161616: - if (modifier == DRM_FORMAT_MOD_LINEAR || - modifier == I915_FORMAT_MOD_X_TILED || - modifier == I915_FORMAT_MOD_Y_TILED) + if (!intel_fb_is_ccs_modifier(modifier)) return true; fallthrough; default: @@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, else fb->modifier = I915_FORMAT_MOD_Y_TILED; break; - case PLANE_CTL_TILED_YF: - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; - else - fb->modifier = I915_FORMAT_MOD_Yf_TILED; + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */ + if (HAS_4TILE(dev_priv)) { + fb->modifier = I915_FORMAT_MOD_4_TILED; + } else { + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; + else + fb->modifier = I915_FORMAT_MOD_Yf_TILED; + } break; default: MISSING_CASE(tiling); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 1bfadd9127fc..3d90bd732e91 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7) #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) +#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile) #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index f01cba4ec283..403d3a581ce7 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -1044,6 +1044,7 @@ static const struct intel_device_info dg2_info = { DGFX_FEATURES, .graphics.rel = 55, .media.rel = 55, + .has_4tile = 1, PLATFORM(INTEL_DG2), .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3450818802c2..22d18a292430 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7284,6 +7284,7 @@ enum { #define PLANE_CTL_TILED_X (1 << 10) #define PLANE_CTL_TILED_Y (4 << 10) #define PLANE_CTL_TILED_YF (5 << 10) +#define PLANE_CTL_TILED_4 (5 << 10) #define PLANE_CTL_ASYNC_FLIP (1 << 9) #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8) #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 669f0d26c3c3..67177e18704a 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -125,6 +125,7 @@ enum intel_ppgtt_type { func(has_64bit_reloc); \ func(gpu_reset_clobbers_display); \ func(has_reset_engine); \ + func(has_4tile); \ func(has_global_mocs); \ func(has_gt_uc); \ func(has_l3_dpf); \ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 01fa3fac1b57..167704f0acf0 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state, } wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED || + modifier == I915_FORMAT_MOD_4_TILED || modifier == I915_FORMAT_MOD_Yf_TILED || modifier == I915_FORMAT_MOD_Y_TILED_CCS || modifier == I915_FORMAT_MOD_Yf_TILED_CCS; diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 7f652c96845b..41184a94935d 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -564,6 +564,14 @@ extern "C" { * pitch is required to be a multiple of 4 tile widths. */ #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) +/* + * Intel F-tiling(aka Tile4) layout + * + * This is a tiled layout using 4Kb tiles in row-major layout. + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD + * (16 bytes) chunks column-major.. + */ +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9) /* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
TileF(Tile4 in bspec) format is 4K tile organized into 64B subtiles with same basic shape as for legacy TileY which will be supported by Display13. v2: - Fixed wrong case condition(Jani Nikula) - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak) v3: - s/I915_TILING_F/TILING_4/g - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g - Removed unneeded fencing code v4: - Rebased, fixed merge conflict with new table-oriented format modifier checking(Stan) - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan) v5: - Still had to remove some Tile F mentionings - Moved has_4tile from adlp to DG2(Ramalingam C) - Check specifically for DG2, but not the Display13(Imre) v6: - Moved Tile4 assocating struct for modifier/display to the beginning(Imre Deak) - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier checks(Imre Deak) - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12 (Imre Deak) v7: - Fixed display_ver to { 13, 13 }(Imre Deak) - Removed redundant newline(Imre Deak) Reviewed-by: Imre Deak <imre.deak@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 1 + drivers/gpu/drm/i915/display/intel_fb.c | 9 +++++++++ drivers/gpu/drm/i915/display/intel_fbc.c | 1 + .../drm/i915/display/intel_plane_initial.c | 1 + .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++-------- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 1 + include/uapi/drm/drm_fourcc.h | 8 ++++++++ 11 files changed, 37 insertions(+), 8 deletions(-)