| Message ID | 20211116062256.2417186-6-vkoul@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/msm: Add Display Stream Compression Support | expand |
On 16/11/2021 09:22, Vinod Koul wrote: > We cannot enable mode_3d when we are using the DSC. So pass > configuration to detect DSC is enabled and not enable mode_3d > when we are using DSC > > We add a helper dpu_encoder_helper_get_dsc() to detect dsc > enabled and pass this to .setup_intf_cfg() > > Signed-off-by: Vinod Koul <vkoul@kernel.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 11 +++++++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 ++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 3 ++- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++ > 4 files changed, 17 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > index e7270eb6b84b..efb85d595598 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > @@ -332,6 +332,17 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( > return BLEND_3D_NONE; > } > > +static inline bool dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc) > +{ > + struct drm_encoder *drm_enc = phys_enc->parent; > + struct msm_drm_private *priv = drm_enc->dev->dev_private; > + > + if (priv->dsc) > + return priv->dsc->dsc_mask; > + > + return 0; > +} > + > /** > * dpu_encoder_helper_split_config - split display configuration helper function > * This helper function may be used by physical encoders to configure > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > index 34a6940d12c5..f3f00f4d0193 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > @@ -70,6 +70,8 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( > intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD; > intf_cfg.stream_sel = cmd_enc->stream_sel; > intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); > + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); > + I'd prefer if we disable mode_3d here, rather than ignoring it in the dpu_hw_ctl_intf_cfg() > ctl->ops.setup_intf_cfg(ctl, &intf_cfg); > } > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > index 64740ddb983e..36831457a91b 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > @@ -519,7 +519,8 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, > > intf_cfg |= (cfg->intf & 0xF) << 4; > > - if (cfg->mode_3d) { > + /* In DSC we can't set merge, so check for dsc too */ > + if (cfg->mode_3d && !cfg->dsc) { I think here'd better have WARN_ON(cfg->mode_3d && cfg->dsc) or similar dev_warn(). > intf_cfg |= BIT(19); > intf_cfg |= (cfg->mode_3d - 0x1) << 20; > } > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > index 806c171e5df2..9847c9c46d6f 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > @@ -40,6 +40,7 @@ struct dpu_hw_stage_cfg { > * @merge_3d: 3d merge block used > * @intf_mode_sel: Interface mode, cmd / vid > * @stream_sel: Stream selection for multi-stream interfaces > + * @dsc: DSC BIT masks > */ > struct dpu_hw_intf_cfg { > enum dpu_intf intf; > @@ -47,6 +48,7 @@ struct dpu_hw_intf_cfg { > enum dpu_merge_3d merge_3d; > enum dpu_ctl_mode_sel intf_mode_sel; > int stream_sel; > + unsigned int dsc; > }; > > /** >
On 16/11/2021 09:22, Vinod Koul wrote: > We cannot enable mode_3d when we are using the DSC. So pass > configuration to detect DSC is enabled and not enable mode_3d > when we are using DSC > > We add a helper dpu_encoder_helper_get_dsc() to detect dsc > enabled and pass this to .setup_intf_cfg() > > Signed-off-by: Vinod Koul <vkoul@kernel.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 11 +++++++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 ++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 3 ++- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++ > 4 files changed, 17 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > index e7270eb6b84b..efb85d595598 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > @@ -332,6 +332,17 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( > return BLEND_3D_NONE; > } > > +static inline bool dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc) > +{ > + struct drm_encoder *drm_enc = phys_enc->parent; > + struct msm_drm_private *priv = drm_enc->dev->dev_private; > + > + if (priv->dsc) > + return priv->dsc->dsc_mask; dsc_mask doesn't exist at this point, so the patch should be moved later in the series. > + > + return 0; > +} > + > /** > * dpu_encoder_helper_split_config - split display configuration helper function > * This helper function may be used by physical encoders to configure > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > index 34a6940d12c5..f3f00f4d0193 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > @@ -70,6 +70,8 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( > intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD; > intf_cfg.stream_sel = cmd_enc->stream_sel; > intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); > + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); > + > ctl->ops.setup_intf_cfg(ctl, &intf_cfg); > } > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > index 64740ddb983e..36831457a91b 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > @@ -519,7 +519,8 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, > > intf_cfg |= (cfg->intf & 0xF) << 4; > > - if (cfg->mode_3d) { > + /* In DSC we can't set merge, so check for dsc too */ > + if (cfg->mode_3d && !cfg->dsc) { > intf_cfg |= BIT(19); > intf_cfg |= (cfg->mode_3d - 0x1) << 20; > } > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > index 806c171e5df2..9847c9c46d6f 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > @@ -40,6 +40,7 @@ struct dpu_hw_stage_cfg { > * @merge_3d: 3d merge block used > * @intf_mode_sel: Interface mode, cmd / vid > * @stream_sel: Stream selection for multi-stream interfaces > + * @dsc: DSC BIT masks > */ > struct dpu_hw_intf_cfg { > enum dpu_intf intf; > @@ -47,6 +48,7 @@ struct dpu_hw_intf_cfg { > enum dpu_merge_3d merge_3d; > enum dpu_ctl_mode_sel intf_mode_sel; > int stream_sel; > + unsigned int dsc; > }; > > /** >
On 16/11/2021 09:22, Vinod Koul wrote: > We cannot enable mode_3d when we are using the DSC. So pass > configuration to detect DSC is enabled and not enable mode_3d > when we are using DSC > > We add a helper dpu_encoder_helper_get_dsc() to detect dsc > enabled and pass this to .setup_intf_cfg() > > Signed-off-by: Vinod Koul <vkoul@kernel.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 11 +++++++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 ++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 3 ++- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++ > 4 files changed, 17 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > index e7270eb6b84b..efb85d595598 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > @@ -332,6 +332,17 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( > return BLEND_3D_NONE; > } > > +static inline bool dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc) > +{ > + struct drm_encoder *drm_enc = phys_enc->parent; > + struct msm_drm_private *priv = drm_enc->dev->dev_private; > + > + if (priv->dsc) > + return priv->dsc->dsc_mask; > + > + return 0; > +} > + > /** > * dpu_encoder_helper_split_config - split display configuration helper function > * This helper function may be used by physical encoders to configure > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > index 34a6940d12c5..f3f00f4d0193 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > @@ -70,6 +70,8 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( > intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD; > intf_cfg.stream_sel = cmd_enc->stream_sel; > intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); > + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); > + You are going to hate me for the comments on this patch. But this chunk should also go into dpu_encoder_phys_vid.c, shouldn't it? > ctl->ops.setup_intf_cfg(ctl, &intf_cfg); > } > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > index 64740ddb983e..36831457a91b 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > @@ -519,7 +519,8 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, > > intf_cfg |= (cfg->intf & 0xF) << 4; > > - if (cfg->mode_3d) { > + /* In DSC we can't set merge, so check for dsc too */ > + if (cfg->mode_3d && !cfg->dsc) { > intf_cfg |= BIT(19); > intf_cfg |= (cfg->mode_3d - 0x1) << 20; > } > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > index 806c171e5df2..9847c9c46d6f 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > @@ -40,6 +40,7 @@ struct dpu_hw_stage_cfg { > * @merge_3d: 3d merge block used > * @intf_mode_sel: Interface mode, cmd / vid > * @stream_sel: Stream selection for multi-stream interfaces > + * @dsc: DSC BIT masks > */ > struct dpu_hw_intf_cfg { > enum dpu_intf intf; > @@ -47,6 +48,7 @@ struct dpu_hw_intf_cfg { > enum dpu_merge_3d merge_3d; > enum dpu_ctl_mode_sel intf_mode_sel; > int stream_sel; > + unsigned int dsc; > }; > > /** >
On Wed, 24 Nov 2021 at 18:40, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > On 16/11/2021 09:22, Vinod Koul wrote: > > We cannot enable mode_3d when we are using the DSC. So pass > > configuration to detect DSC is enabled and not enable mode_3d > > when we are using DSC > > > > We add a helper dpu_encoder_helper_get_dsc() to detect dsc > > enabled and pass this to .setup_intf_cfg() > > > > Signed-off-by: Vinod Koul <vkoul@kernel.org> > > --- > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 11 +++++++++++ > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 ++ > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 3 ++- > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++ > > 4 files changed, 17 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > > index e7270eb6b84b..efb85d595598 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > > @@ -332,6 +332,17 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( > > return BLEND_3D_NONE; > > } > > > > +static inline bool dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc) Here you are returning the mask, so it should not be bool. > > +{ > > + struct drm_encoder *drm_enc = phys_enc->parent; > > + struct msm_drm_private *priv = drm_enc->dev->dev_private; > > + > > + if (priv->dsc) > > + return priv->dsc->dsc_mask; > > dsc_mask doesn't exist at this point, so the patch should be moved later > in the series. Please ignore this comment, dsc mask already exists. > > > + > > + return 0; > > +} > > + > > /** > > * dpu_encoder_helper_split_config - split display configuration helper function > > * This helper function may be used by physical encoders to configure > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > > index 34a6940d12c5..f3f00f4d0193 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > > @@ -70,6 +70,8 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( > > intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD; > > intf_cfg.stream_sel = cmd_enc->stream_sel; > > intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); > > + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); > > + > > ctl->ops.setup_intf_cfg(ctl, &intf_cfg); > > } > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > > index 64740ddb983e..36831457a91b 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > > @@ -519,7 +519,8 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, > > > > intf_cfg |= (cfg->intf & 0xF) << 4; > > > > - if (cfg->mode_3d) { > > + /* In DSC we can't set merge, so check for dsc too */ > > + if (cfg->mode_3d && !cfg->dsc) { > > intf_cfg |= BIT(19); > > intf_cfg |= (cfg->mode_3d - 0x1) << 20; > > } > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > > index 806c171e5df2..9847c9c46d6f 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h > > @@ -40,6 +40,7 @@ struct dpu_hw_stage_cfg { > > * @merge_3d: 3d merge block used > > * @intf_mode_sel: Interface mode, cmd / vid > > * @stream_sel: Stream selection for multi-stream interfaces > > + * @dsc: DSC BIT masks > > */ > > struct dpu_hw_intf_cfg { > > enum dpu_intf intf; > > @@ -47,6 +48,7 @@ struct dpu_hw_intf_cfg { > > enum dpu_merge_3d merge_3d; > > enum dpu_ctl_mode_sel intf_mode_sel; > > int stream_sel; > > + unsigned int dsc; > > }; > >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index e7270eb6b84b..efb85d595598 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -332,6 +332,17 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( return BLEND_3D_NONE; } +static inline bool dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc) +{ + struct drm_encoder *drm_enc = phys_enc->parent; + struct msm_drm_private *priv = drm_enc->dev->dev_private; + + if (priv->dsc) + return priv->dsc->dsc_mask; + + return 0; +} + /** * dpu_encoder_helper_split_config - split display configuration helper function * This helper function may be used by physical encoders to configure diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 34a6940d12c5..f3f00f4d0193 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -70,6 +70,8 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD; intf_cfg.stream_sel = cmd_enc->stream_sel; intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); + ctl->ops.setup_intf_cfg(ctl, &intf_cfg); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 64740ddb983e..36831457a91b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -519,7 +519,8 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, intf_cfg |= (cfg->intf & 0xF) << 4; - if (cfg->mode_3d) { + /* In DSC we can't set merge, so check for dsc too */ + if (cfg->mode_3d && !cfg->dsc) { intf_cfg |= BIT(19); intf_cfg |= (cfg->mode_3d - 0x1) << 20; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index 806c171e5df2..9847c9c46d6f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -40,6 +40,7 @@ struct dpu_hw_stage_cfg { * @merge_3d: 3d merge block used * @intf_mode_sel: Interface mode, cmd / vid * @stream_sel: Stream selection for multi-stream interfaces + * @dsc: DSC BIT masks */ struct dpu_hw_intf_cfg { enum dpu_intf intf; @@ -47,6 +48,7 @@ struct dpu_hw_intf_cfg { enum dpu_merge_3d merge_3d; enum dpu_ctl_mode_sel intf_mode_sel; int stream_sel; + unsigned int dsc; }; /**
We cannot enable mode_3d when we are using the DSC. So pass configuration to detect DSC is enabled and not enable mode_3d when we are using DSC We add a helper dpu_encoder_helper_get_dsc() to detect dsc enabled and pass this to .setup_intf_cfg() Signed-off-by: Vinod Koul <vkoul@kernel.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 11 +++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++ 4 files changed, 17 insertions(+), 1 deletion(-)