| Message ID | 20211123193649.3153258-3-uma.shankar@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable pipe color support on D13 platform | expand |
On Wed, Nov 24, 2021 at 01:06:48AM +0530, Uma Shankar wrote: > Enable Pipe Degamma for XE_LPD. Extend the legacy implementation > to incorparate the extended lut size for XE_LPD. > > Signed-off-by: Uma Shankar <uma.shankar@intel.com> > --- > drivers/gpu/drm/i915/display/intel_color.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c > index e529dbeee525..81046d5ab509 100644 > --- a/drivers/gpu/drm/i915/display/intel_color.c > +++ b/drivers/gpu/drm/i915/display/intel_color.c > @@ -815,6 +815,12 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) > enum pipe pipe = crtc->pipe; > int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; > const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data; > + u32 extended_lut_size; > + > + if (DISPLAY_VER(dev_priv) >= 13) > + extended_lut_size = 131; > + else > + extended_lut_size = 35; Can you extract that into a small helper? IIRC I did that for the internal version already. > > /* > * When setting the auto-increment bit, the hardware seems to > @@ -827,8 +833,8 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) > > for (i = 0; i < lut_size; i++) { > /* > - * First 33 entries represent range from 0 to 1.0 > - * 34th and 35th entry will represent extended range > + * First lut_size entries represent range from 0 to 1.0 > + * 3 additional lut entries will represent extended range > * inputs 3.0 and 7.0 respectively, currently clamped > * at 1.0. Since the precision is 16bit, the user > * value can be directly filled to register. > @@ -844,7 +850,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) > } > > /* Clamp values > 1.0. */ > - while (i++ < 35) > + while (i++ < extended_lut_size) > intel_de_write_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16); > > intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0); > -- > 2.25.1
> -----Original Message----- > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > Sent: Wednesday, November 24, 2021 8:23 PM > To: Shankar, Uma <uma.shankar@intel.com> > Cc: intel-gfx@lists.freedesktop.org; =ville.syrjala@linux.intel.com > Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915/xelpd: Enable Pipe Degamma > > On Wed, Nov 24, 2021 at 01:06:48AM +0530, Uma Shankar wrote: > > Enable Pipe Degamma for XE_LPD. Extend the legacy implementation to > > incorparate the extended lut size for XE_LPD. > > > > Signed-off-by: Uma Shankar <uma.shankar@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_color.c | 12 +++++++++--- > > 1 file changed, 9 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c > > b/drivers/gpu/drm/i915/display/intel_color.c > > index e529dbeee525..81046d5ab509 100644 > > --- a/drivers/gpu/drm/i915/display/intel_color.c > > +++ b/drivers/gpu/drm/i915/display/intel_color.c > > @@ -815,6 +815,12 @@ static void glk_load_degamma_lut(const struct > intel_crtc_state *crtc_state) > > enum pipe pipe = crtc->pipe; > > int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; > > const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data; > > + u32 extended_lut_size; > > + > > + if (DISPLAY_VER(dev_priv) >= 13) > > + extended_lut_size = 131; > > + else > > + extended_lut_size = 35; > > Can you extract that into a small helper? IIRC I did that for the internal version > already. Ok sure, will update this. Regards, Uma Shankar > > > > /* > > * When setting the auto-increment bit, the hardware seems to @@ > > -827,8 +833,8 @@ static void glk_load_degamma_lut(const struct > > intel_crtc_state *crtc_state) > > > > for (i = 0; i < lut_size; i++) { > > /* > > - * First 33 entries represent range from 0 to 1.0 > > - * 34th and 35th entry will represent extended range > > + * First lut_size entries represent range from 0 to 1.0 > > + * 3 additional lut entries will represent extended range > > * inputs 3.0 and 7.0 respectively, currently clamped > > * at 1.0. Since the precision is 16bit, the user > > * value can be directly filled to register. > > @@ -844,7 +850,7 @@ static void glk_load_degamma_lut(const struct > intel_crtc_state *crtc_state) > > } > > > > /* Clamp values > 1.0. */ > > - while (i++ < 35) > > + while (i++ < extended_lut_size) > > intel_de_write_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16); > > > > intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0); > > -- > > 2.25.1 > > -- > Ville Syrjälä > Intel
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index e529dbeee525..81046d5ab509 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -815,6 +815,12 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) enum pipe pipe = crtc->pipe; int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data; + u32 extended_lut_size; + + if (DISPLAY_VER(dev_priv) >= 13) + extended_lut_size = 131; + else + extended_lut_size = 35; /* * When setting the auto-increment bit, the hardware seems to @@ -827,8 +833,8 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) for (i = 0; i < lut_size; i++) { /* - * First 33 entries represent range from 0 to 1.0 - * 34th and 35th entry will represent extended range + * First lut_size entries represent range from 0 to 1.0 + * 3 additional lut entries will represent extended range * inputs 3.0 and 7.0 respectively, currently clamped * at 1.0. Since the precision is 16bit, the user * value can be directly filled to register. @@ -844,7 +850,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) } /* Clamp values > 1.0. */ - while (i++ < 35) + while (i++ < extended_lut_size) intel_de_write_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16); intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
Enable Pipe Degamma for XE_LPD. Extend the legacy implementation to incorparate the extended lut size for XE_LPD. Signed-off-by: Uma Shankar <uma.shankar@intel.com> --- drivers/gpu/drm/i915/display/intel_color.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-)