| Message ID | 1637299488-22336-1-git-send-email-pillair@codeaurora.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v7] arm64: dts: qcom: sc7280: Add WPSS remoteproc node | expand |
Hey Rakesh, On 2021-11-19 10:54, Rakesh Pillai wrote: > Add the WPSS remoteproc node in dts for > PIL loading. > > Reviewed-by: Stephen Boyd <swboyd@chromium.org> > Signed-off-by: Rakesh Pillai <pillair@codeaurora.org> > --- > Changes from v6: > - Swap the oder of two properties in wpss_mem reserved memory > > Changes from v5: > - Update the clock names > --- > arch/arm64/boot/dts/qcom/sc7280-idp.dts | 4 +++ > arch/arm64/boot/dts/qcom/sc7280.dtsi | 56 > +++++++++++++++++++++++++++++++++ > 2 files changed, 60 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts > b/arch/arm64/boot/dts/qcom/sc7280-idp.dts > index 9b991ba..ddab150 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts > @@ -80,3 +80,7 @@ > qcom,pre-scaling = <1 1>; > }; > }; > + > +&remoteproc_wpss { > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi > b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 365a2e0..dd93f13 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -134,6 +134,11 @@ > no-map; > }; > > + wpss_mem: memory@9ae00000 { > + reg = <0x0 0x9ae00000 0x0 0x1900000>; > + no-map; > + }; > + wpss_mem is already part of idp board dts. We no longer include PIL reserved memory regions in the base SoC dtsi since the size varies across boards. > rmtfs_mem: memory@9c900000 { > compatible = "qcom,rmtfs-mem"; > reg = <0x0 0x9c900000 0x0 0x280000>; > @@ -2598,6 +2603,57 @@ > status = "disabled"; > }; > > + remoteproc_wpss: remoteproc@8a00000 { > + compatible = "qcom,sc7280-wpss-pil"; > + reg = <0 0x08a00000 0 0x10000>; > + > + interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, > + <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, > + <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, > + <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, > + <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, > + <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "wdog", "fatal", "ready", "handover", > + "stop-ack", "shutdown-ack"; > + > + clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, > + <&gcc GCC_WPSS_AHB_CLK>, > + <&gcc GCC_WPSS_RSCP_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "ahb_bdg", "ahb", > + "rscp", "xo"; > + > + power-domains = <&rpmhpd SC7280_CX>, > + <&rpmhpd SC7280_MX>; > + power-domain-names = "cx", "mx"; > + > + memory-region = <&wpss_mem>; > + > + qcom,qmp = <&aoss_qmp>; > + > + qcom,smem-states = <&wpss_smp2p_out 0>; > + qcom,smem-state-names = "stop"; > + > + resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, > + <&pdc_reset PDC_WPSS_SYNC_RESET>; > + reset-names = "restart", "pdc_sync"; > + > + qcom,halt-regs = <&tcsr_mutex 0x37000>; > + > + status = "disabled"; > + > + glink-edge { > + interrupts-extended = <&ipcc IPCC_CLIENT_WPSS > + IPCC_MPROC_SIGNAL_GLINK_QMP > + IRQ_TYPE_EDGE_RISING>; > + mboxes = <&ipcc IPCC_CLIENT_WPSS > + IPCC_MPROC_SIGNAL_GLINK_QMP>; > + > + label = "wpss"; > + qcom,remote-pid = <13>; > + }; > + }; > + > dc_noc: interconnect@90e0000 { > reg = <0 0x090e0000 0 0x5080>; > compatible = "qcom,sc7280-dc-noc";
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 9b991ba..ddab150 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -80,3 +80,7 @@ qcom,pre-scaling = <1 1>; }; }; + +&remoteproc_wpss { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 365a2e0..dd93f13 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -134,6 +134,11 @@ no-map; }; + wpss_mem: memory@9ae00000 { + reg = <0x0 0x9ae00000 0x0 0x1900000>; + no-map; + }; + rmtfs_mem: memory@9c900000 { compatible = "qcom,rmtfs-mem"; reg = <0x0 0x9c900000 0x0 0x280000>; @@ -2598,6 +2603,57 @@ status = "disabled"; }; + remoteproc_wpss: remoteproc@8a00000 { + compatible = "qcom,sc7280-wpss-pil"; + reg = <0 0x08a00000 0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, + <&gcc GCC_WPSS_AHB_CLK>, + <&gcc GCC_WPSS_RSCP_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ahb_bdg", "ahb", + "rscp", "xo"; + + power-domains = <&rpmhpd SC7280_CX>, + <&rpmhpd SC7280_MX>; + power-domain-names = "cx", "mx"; + + memory-region = <&wpss_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&wpss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, + <&pdc_reset PDC_WPSS_SYNC_RESET>; + reset-names = "restart", "pdc_sync"; + + qcom,halt-regs = <&tcsr_mutex 0x37000>; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "wpss"; + qcom,remote-pid = <13>; + }; + }; + dc_noc: interconnect@90e0000 { reg = <0 0x090e0000 0 0x5080>; compatible = "qcom,sc7280-dc-noc";