| Message ID | 1638179932-3353-2-git-send-email-srivasam@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add pin control support for lpass sc7280 | expand |
On Mon, 29 Nov 2021 15:28:48 +0530, Srinivasa Rao Mandadapu wrote: > Change generic lpass lpi pincotrol bindings file to SoC specific file, > to distinguish and accomadate other SoC specific dt bindings. > > Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> > Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org> > Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org> > --- > .../bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 130 --------------------- > .../pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml | 130 +++++++++++++++++++++ > 2 files changed, 130 insertions(+), 130 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml > create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: ./Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml: $id: relative path/filename doesn't match actual path or filename expected: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml# doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1561071 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On 29/11/2021 09:58, Srinivasa Rao Mandadapu wrote: > Change generic lpass lpi pincotrol bindings file to SoC specific file, > to distinguish and accomadate other SoC specific dt bindings. TBH, for adding sc7820 lpass lpi support, this rename patch is totally not necessary. > > Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> > Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org> > Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org> > --- > .../bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 130 --------------------- > .../pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml | 130 +++++++++++++++++++++ Consider using "git mv" when renaming files, this would give a better diff stat. --srini > 2 files changed, 130 insertions(+), 130 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml > create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml > deleted file mode 100644 > index e47ebf9..0000000 > --- a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml > +++ /dev/null > @@ -1,130 +0,0 @@ > -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > -%YAML 1.2 > ---- > -$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml# > -$schema: http://devicetree.org/meta-schemas/core.yaml# > - > -title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS) > - Low Power Island (LPI) TLMM block > - > -maintainers: > - - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> > - > -description: | > - This binding describes the Top Level Mode Multiplexer block found in the > - LPASS LPI IP on most Qualcomm SoCs > - > -properties: > - compatible: > - const: qcom,sm8250-lpass-lpi-pinctrl > - > - reg: > - minItems: 2 > - maxItems: 2 > - > - clocks: > - items: > - - description: LPASS Core voting clock > - - description: LPASS Audio voting clock > - > - clock-names: > - items: > - - const: core > - - const: audio > - > - gpio-controller: true > - > - '#gpio-cells': > - description: Specifying the pin number and flags, as defined in > - include/dt-bindings/gpio/gpio.h > - const: 2 > - > - gpio-ranges: > - maxItems: 1 > - > -#PIN CONFIGURATION NODES > -patternProperties: > - '-pins$': > - type: object > - description: > - Pinctrl node's client devices use subnodes for desired pin configuration. > - Client device subnodes use below standard properties. > - $ref: "/schemas/pinctrl/pincfg-node.yaml" > - > - properties: > - pins: > - description: > - List of gpio pins affected by the properties specified in this > - subnode. > - items: > - oneOf: > - - pattern: "^gpio([0-9]|[1-9][0-9])$" > - minItems: 1 > - maxItems: 14 > - > - function: > - enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws, > - qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk, > - dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data, > - i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk, > - dmic3_data, i2s2_data ] > - description: > - Specify the alternative function to be configured for the specified > - pins. > - > - drive-strength: > - enum: [2, 4, 6, 8, 10, 12, 14, 16] > - default: 2 > - description: > - Selects the drive strength for the specified pins, in mA. > - > - slew-rate: > - enum: [0, 1, 2, 3] > - default: 0 > - description: | > - 0: No adjustments > - 1: Higher Slew rate (faster edges) > - 2: Lower Slew rate (slower edges) > - 3: Reserved (No adjustments) > - > - bias-pull-down: true > - > - bias-pull-up: true > - > - bias-disable: true > - > - output-high: true > - > - output-low: true > - > - required: > - - pins > - - function > - > - additionalProperties: false > - > -required: > - - compatible > - - reg > - - clocks > - - clock-names > - - gpio-controller > - - '#gpio-cells' > - - gpio-ranges > - > -additionalProperties: false > - > -examples: > - - | > - #include <dt-bindings/sound/qcom,q6afe.h> > - lpi_tlmm: pinctrl@33c0000 { > - compatible = "qcom,sm8250-lpass-lpi-pinctrl"; > - reg = <0x33c0000 0x20000>, > - <0x3550000 0x10000>; > - clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > - <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; > - clock-names = "core", "audio"; > - gpio-controller; > - #gpio-cells = <2>; > - gpio-ranges = <&lpi_tlmm 0 0 14>; > - }; > diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml > new file mode 100644 > index 0000000..e47ebf9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml > @@ -0,0 +1,130 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS) > + Low Power Island (LPI) TLMM block > + > +maintainers: > + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> > + > +description: | > + This binding describes the Top Level Mode Multiplexer block found in the > + LPASS LPI IP on most Qualcomm SoCs > + > +properties: > + compatible: > + const: qcom,sm8250-lpass-lpi-pinctrl > + > + reg: > + minItems: 2 > + maxItems: 2 > + > + clocks: > + items: > + - description: LPASS Core voting clock > + - description: LPASS Audio voting clock > + > + clock-names: > + items: > + - const: core > + - const: audio > + > + gpio-controller: true > + > + '#gpio-cells': > + description: Specifying the pin number and flags, as defined in > + include/dt-bindings/gpio/gpio.h > + const: 2 > + > + gpio-ranges: > + maxItems: 1 > + > +#PIN CONFIGURATION NODES > +patternProperties: > + '-pins$': > + type: object > + description: > + Pinctrl node's client devices use subnodes for desired pin configuration. > + Client device subnodes use below standard properties. > + $ref: "/schemas/pinctrl/pincfg-node.yaml" > + > + properties: > + pins: > + description: > + List of gpio pins affected by the properties specified in this > + subnode. > + items: > + oneOf: > + - pattern: "^gpio([0-9]|[1-9][0-9])$" > + minItems: 1 > + maxItems: 14 > + > + function: > + enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws, > + qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk, > + dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data, > + i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk, > + dmic3_data, i2s2_data ] > + description: > + Specify the alternative function to be configured for the specified > + pins. > + > + drive-strength: > + enum: [2, 4, 6, 8, 10, 12, 14, 16] > + default: 2 > + description: > + Selects the drive strength for the specified pins, in mA. > + > + slew-rate: > + enum: [0, 1, 2, 3] > + default: 0 > + description: | > + 0: No adjustments > + 1: Higher Slew rate (faster edges) > + 2: Lower Slew rate (slower edges) > + 3: Reserved (No adjustments) > + > + bias-pull-down: true > + > + bias-pull-up: true > + > + bias-disable: true > + > + output-high: true > + > + output-low: true > + > + required: > + - pins > + - function > + > + additionalProperties: false > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - gpio-controller > + - '#gpio-cells' > + - gpio-ranges > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/sound/qcom,q6afe.h> > + lpi_tlmm: pinctrl@33c0000 { > + compatible = "qcom,sm8250-lpass-lpi-pinctrl"; > + reg = <0x33c0000 0x20000>, > + <0x3550000 0x10000>; > + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; > + clock-names = "core", "audio"; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&lpi_tlmm 0 0 14>; > + }; >
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml deleted file mode 100644 index e47ebf9..0000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml +++ /dev/null @@ -1,130 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS) - Low Power Island (LPI) TLMM block - -maintainers: - - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> - -description: | - This binding describes the Top Level Mode Multiplexer block found in the - LPASS LPI IP on most Qualcomm SoCs - -properties: - compatible: - const: qcom,sm8250-lpass-lpi-pinctrl - - reg: - minItems: 2 - maxItems: 2 - - clocks: - items: - - description: LPASS Core voting clock - - description: LPASS Audio voting clock - - clock-names: - items: - - const: core - - const: audio - - gpio-controller: true - - '#gpio-cells': - description: Specifying the pin number and flags, as defined in - include/dt-bindings/gpio/gpio.h - const: 2 - - gpio-ranges: - maxItems: 1 - -#PIN CONFIGURATION NODES -patternProperties: - '-pins$': - type: object - description: - Pinctrl node's client devices use subnodes for desired pin configuration. - Client device subnodes use below standard properties. - $ref: "/schemas/pinctrl/pincfg-node.yaml" - - properties: - pins: - description: - List of gpio pins affected by the properties specified in this - subnode. - items: - oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9])$" - minItems: 1 - maxItems: 14 - - function: - enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws, - qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk, - dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data, - i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk, - dmic3_data, i2s2_data ] - description: - Specify the alternative function to be configured for the specified - pins. - - drive-strength: - enum: [2, 4, 6, 8, 10, 12, 14, 16] - default: 2 - description: - Selects the drive strength for the specified pins, in mA. - - slew-rate: - enum: [0, 1, 2, 3] - default: 0 - description: | - 0: No adjustments - 1: Higher Slew rate (faster edges) - 2: Lower Slew rate (slower edges) - 3: Reserved (No adjustments) - - bias-pull-down: true - - bias-pull-up: true - - bias-disable: true - - output-high: true - - output-low: true - - required: - - pins - - function - - additionalProperties: false - -required: - - compatible - - reg - - clocks - - clock-names - - gpio-controller - - '#gpio-cells' - - gpio-ranges - -additionalProperties: false - -examples: - - | - #include <dt-bindings/sound/qcom,q6afe.h> - lpi_tlmm: pinctrl@33c0000 { - compatible = "qcom,sm8250-lpass-lpi-pinctrl"; - reg = <0x33c0000 0x20000>, - <0x3550000 0x10000>; - clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; - clock-names = "core", "audio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&lpi_tlmm 0 0 14>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml new file mode 100644 index 0000000..e47ebf9 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS) + Low Power Island (LPI) TLMM block + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + LPASS LPI IP on most Qualcomm SoCs + +properties: + compatible: + const: qcom,sm8250-lpass-lpi-pinctrl + + reg: + minItems: 2 + maxItems: 2 + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9])$" + minItems: 1 + maxItems: 14 + + function: + enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws, + qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk, + dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data, + i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk, + dmic3_data, i2s2_data ] + description: + Specify the alternative function to be configured for the specified + pins. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + slew-rate: + enum: [0, 1, 2, 3] + default: 0 + description: | + 0: No adjustments + 1: Higher Slew rate (faster edges) + 2: Lower Slew rate (slower edges) + 3: Reserved (No adjustments) + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/sound/qcom,q6afe.h> + lpi_tlmm: pinctrl@33c0000 { + compatible = "qcom,sm8250-lpass-lpi-pinctrl"; + reg = <0x33c0000 0x20000>, + <0x3550000 0x10000>; + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 14>; + };